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Registered: ‎06-08-2018

using FPGA Editor in partial reconfiguration flow

Dear all, 

I find this option in FPGA editor tutorial that it's possible to add a new net to the database but the all selected component pins must not belong to any other nets. according to that, is it possible to add a new net between two component pin of two different partial reconfiguration module?
In other words, is it possible to add a new route between two partial reconfiguration partitions by using FPGA editor?

I think it can't be possible due to this reason that making a change in routing between two partitions, will change the bitstream of the static part and it's in contradiction with the nature of the static part.  it would be very kind of you if you guided me through this.

Best Regards 

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Xilinx Employee
Xilinx Employee
Registered: ‎11-17-2008

Re: using FPGA Editor in partial reconfiguration flow

Yes, you are correct: Any change in FPGA Editor to the static part of the design would only change that design image, so any other configuration of the design would not have this change, and resulting bitstreams would no longer be compatible.  Now if you could make this same edit to every configuration of the design and guarantee each change was identical, then you could still be fine, but I would strongly recommend returning to the standard tool flow and apply the change in the source netlist (via synthesis) and then lock and propagate the change through all configurations using the standard approach.  And definitely continue to use PR Verify to ensure all configurations remain in sync.