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Observer jiang1
Observer
9,469 Views
Registered: ‎06-20-2013

virtex 6 partial reconfiguration of MIG controller

divice:virtex 6 vlx240t

ISE:14.5

PlanAhead:14.5

 

In my project, generate MIG controller CORE that is static module and partial module is LED flash,;so the static ngc is top.ngc  and the partial ngc is led.ngc;  I learn to ug702.pdf and flow the design; when I select Open Synthesized Design,the tool PlanAhead 14.5 is closed; I try many times and always the same;  the warning : Abnormal program termination <EXCEPTION_ACCES_VIOLATION>;

 

I think about the assign IP restrictions may occure due to components used to implement the IP .Examples include :ChipScope ICON  ,  EDK blocks ,  MIG controller(MMCM)  in  the ug702.pdf page 17.

is that mean MIG core can't be used in partial reconfiguration project?

I already try many ways and failed.

 

who can suggest some ideas and help me ?

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Xilinx Employee
Xilinx Employee
9,379 Views
Registered: ‎10-24-2013

Re: virtex 6 partial reconfiguration of MIG controller

Hi
Moving to Design entry board.
Thanks,Vijay
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