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Adventurer
Adventurer
999 Views
Registered: ‎05-16-2014

ChipScope Not being PAR

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Spartan 6 -- XC6SLX100T

 

We use scripts at RMS. Synplify Pro is used for the synthesis. For this project ISE is used for the MAP,, PAR etc

I have a simple ICON with one control. An ILA with 8 Triggers ports each with only 1 bit.

Instantiations in one file.

The ICON and ILA are declared as components. Both have the attributes of

syn_black_box and syn_noprune,.  Synplify Pro finds both and all is well. We checked the log file.

 

When ISE takes over it fails. It complains about the instantiation name.

 

The instantiation is as follows:

chipscope_icon_inst : chipscope_icon

port map( CONTROL => cscontrol);

 

chipscope_ila_inst : chipscope_ila

port map( CONTROL => cscontrol,

                CLK => clk,

                TRIG0 => trig0,

                TRIG1 => trig1,

                ...   );

 

Any idea? Are there some switches that have to be set? If Synplify Pro finds everything why doesn't ISE 14.7?

 

My knowledge is that if you declare the component the library is not required in the instantiation. Our scripts have

another file used for accessing the core generated files.

 

Also, even if I use the library in the instantiations Chipscope is not put into the code.

 

chipscope_icon : entity project_lib.chipscope_icon

port map( CONTROL => control);

 

 

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Adventurer
Adventurer
1,191 Views
Registered: ‎05-16-2014

Re: ChipScope Not being PAR

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Found the problem. It was an internal error in one of our scripts.

 

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6 Replies
Moderator
Moderator
941 Views
Registered: ‎02-09-2017

Re: ChipScope Not being PAR

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HI @swimteam,

 

Could you please post the error that you see with ISE? The description and code number may help us to narrow down the issue.

 

Also, what version of Synplify Pro and ISE are you using?

 

Finally, did you apply the mark_debug constraint to the nets connect to the ILA? I'm wondering if during the place and route those nets are getting optimized out and consequently the ILA getting removed.

 

Thanks.

Andre Guerrero

Product Applications Engineer

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Adventurer
Adventurer
929 Views
Registered: ‎05-16-2014

Re: ChipScope Not being PAR

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The errors are:

 

ERROR:NgdBuild:604 - logical block
   'fpga_core_inst/chipscope_ila0_Inst' with type
   'chipscope_ila0' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'chipscope_ila0' is not supported in target 'spartan6'.
ERROR:NgdBuild:604 - logical block
   'fpga_core_inst/chipscope_icon0_Inst' with type
   'chipscope_icon0' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'chipscope_icon0' is not supported in target 'spartan6'.

 

ISE 14.7

 

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Adventurer
Adventurer
916 Views
Registered: ‎05-16-2014

Re: ChipScope Not being PAR

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I have regenerated the ICON and ILA cores and made sure all files are in the area that ISE can get to.

 

Still fails in the translate.

 

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Moderator
Moderator
910 Views
Registered: ‎02-09-2017

Re: ChipScope Not being PAR

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Hi @swimteam,

 

I suspect that the issue might still be with the files for the Chipscope instantiation.

The two main causes for these issues are:

 

  • Module or macro that is called out or used by the top-level design or netlist is not located in the same working directory.

 

  • The signal names on the module or macro do not match the signal names in the top-level design or netlist.

 

Please take a look at these three ARs which threat the same error code.

 

https://www.xilinx.com/support/answers/13867.html

 

https://www.xilinx.com/support/answers/11701.html

 

https://www.xilinx.com/support/answers/45628.html

 

 

Please let us know if you have any questions or still find issues.

 

Thanks.

Andre Guerrero

Product Applications Engineer

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Adventurer
Adventurer
887 Views
Registered: ‎05-16-2014

Re: ChipScope Not being PAR

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I will take a look at the 3 links. In the meantime, here are the errors.

Again, all files generated are in the area that ISE can get access. Such a simple debug.

Each Trig is only 1 std_logic signal. ILA control goes to ICON control. Nothing more.

 

ERROR:NgdBuild:604 - logical block
   'fpga_core_inst/chipscope_icon0_Inst' with type
   'chipscope_icon0' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'chipscope_icon0' is not supported in target 'spartan6'.
ERROR:NgdBuild:456 - logical net 'fpga_core_inst/iconControl0(3)'
   has both active and tristate drivers...
   Active driver(s) of net 'fpga_core_inst/iconControl0(3)':

 -----------------
   'O' pin on block
   'fpga_core_inst/chipscope_ila0_Inst/U0/I_NO_D.U_ILA/U_DOUT' (
   LUT3 )
   Tristate driver(s) of net 'fpga_core_inst/iconControl0(3)':
   -------------------
   'CONTROL0(3)' pin on block
   'fpga_core_inst/chipscope_icon0_Inst' ( chipscope_icon0 )

 

 

Something else must be missing that ISE is looking for. Don't know what.

 

Swimteam

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Adventurer
Adventurer
1,192 Views
Registered: ‎05-16-2014

Re: ChipScope Not being PAR

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Found the problem. It was an internal error in one of our scripts.

 

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