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Observer baldrik
Observer
5,249 Views
Registered: ‎06-04-2010

Chipscope Pro startup trigger how to?

Hi,

 

I am using ISE 14.7 and Windows 7 Pro and a ML605 dev board. I am having trouble figuring out how to use chipscope's startup trigger.

 

I am using the file below to test.

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library tes;


entity ml605_startup_test is
port (
  sys_clk_p:in std_logic;
  sys_clk_n:in std_logic
);
end entity ml605_startup_test;

architecture RTL of ml605_startup_test is
component clk_wiz_v3_6_0
port
 (-- Clock in ports
  CLK_IN1_P:in std_logic;
  CLK_IN1_N:in std_logic;
  -- Clock out ports
  CLK_OUT1:out std_logic;
  -- Status and control signals
  RESET:in std_logic;
  LOCKED:out std_logic
 );
end component;
  
signal boot_clk:std_logic;

signal counter:unsigned(15 downto 0);
signal locked:std_logic;
signal reset:std_logic;

attribute S:string;
attribute S of counter:signal is "TRUE";

attribute MARK_DEBUG:string;
attribute MARK_DEBUG of counter:signal is "TRUE";
attribute MARK_DEBUG of reset:signal is "TRUE";
begin

MMCM:clk_wiz_v3_6_0
  port map
   (-- Clock in ports
    CLK_IN1_P => sys_clk_p,
    CLK_IN1_N => sys_clk_n,
    -- Clock out ports
    CLK_OUT1 => boot_clk,
    -- Status and control signals
    RESET  => '0',
    LOCKED => locked);

glbl_reset_gen:entity tes.reset_sync
port map(
  clk => boot_clk,
  enable => locked,
  reset_in => '0',
  reset_out => reset
);

test:process (boot_clk) is
begin
  if rising_edge(boot_clk) then
    if reset='1' then
      counter <= (others => '0');
    else
      counter <= counter+1;
    end if;
  end if;
end process test;

end architecture RTL;

Where the MMCM (clock wiz) generates a 250 MHz clock from the onboard 200Mhz differential clock and the reset sync is a simple 2FF synchroniser with clock enables connected to the locked output of the MMCM.

 

I follow the directions in UG029.

In single trigger mode I set the trigger to fire when counter=0x8000.

Then save the startup trigger files.

I reimplement the design after adding the generated UCF.

I use Chipscope analyser to program the bit stream then use startup trigger mode (loading saved startupfiles) press run but there is no trigger.

 

After reading this post I tried putting chipscope analyser in to startup trigger mode pressing the run button (analyser displays "waiting for core to be armed"), then using impact to program the FPGA with the bitstream after which analyser displays "0 samples in buffer" and never triggers. 

 

Either way going back to single trigger and hitting run the core triggers and presents the correct captured data.

 

What am I doing wrong? Is the simple example code not appropriate for startup trigger mode? Any Ideas?

 

Thanks

baldrik.

 

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