12-19-2013 03:41 AM
I need some urgent help on this chipscope issue I am facing.
Previously I had used chipscope by inserting core in Navigator (RTL, prior to synthesis), or on ngc file. this time, due to vendor flow, i must instantiate the ICON and ILA in RTL and then implement it. I cannto use Navigator due to this vendor flow that we must follow. Vendor flow is makefile based.
so I created the core in a directory, then instantiated just the module. in the RTL, for translate I give the search path where ngc files are present
Problem I am facing is - when I download the code using Impact then open the cable through Analyzer, it is not detecting any core. If I download the bit file also with Analyzer, it detects the core, but it does not trigger - even with immediate trigger option - showing slow or stopped clock.
I confirmed that ILA is present using FPGA editor.
One issue I onserved is vendor supplied system is targetted for 10ns main clock, the moment I insert chipscope , it violates the clock by 1.5 to 2+ ns. Could this give a stopped clock issue ?
Another point is when I create ICON, it gives the control port as inout - is this an issues ? It should have been only an output ? Chipscope_ila_tut.pdf ( Page 6) is giving this port as output only.
I have confirmed the flow is OK , on a small test design, though using a Navigator project- so it is not that I miss something very grave.
I have gone through AR19337, and those all are ok in my case
My RTL is as below. ------------------------------
main code body is like this, in the same file, I have defined modules of ICON and ILA.
port wire,reg etc.
// custom Logic for which I need to put scope
always @(posedge clk)
duc_enb_reg <= 1'b0 ;
dac_reg <= 4'h0 ;
duc_enb_reg <= duc_enb ;
dac_reg <= da_c ;
chipscope_icon chipscope_icon (
.CONTROL0 (CONTROL0 )
chipscope_ila chipscope_ila (
.CONTROL ( CONTROL0) ,
.TRIG0 ( dac_reg)
endmodule // dsp_core
module chipscope_ila (
CLK, CONTROL, TRIG0
inout [35 : 0] CONTROL;
input [7 : 0] TRIG0;
module chipscope_icon (
inout [35 : 0] CONTROL0; // this was inout, ch
12-23-2013 09:26 PM
I have an update. I took simple MAP commands from a another example code and did a map onwards, and then chipscope core detected and I am able to make a immediate trigger. Now a new problem started. Ethernet is not being detected by a computer. Ethernet is the only way to communicate with my design.
this was the original Map commands where it did not detect the chipscopre core, but it did detect Ethernet.
map -intstyle ise -p xc3sd3400a-fg676-5 -timing -logic_opt on -ol high -xe n -t 1 -register_duplication on -cm speed -detail -ir off -ignore_keep_hierarchy -pr off -power off -o xxxx.ncd xxxx.ngd xxxx.pcf
but when I gave this simple command, it detected chipscope core, but ethernet was not detected.
map -intstyle ise -p xc3sd3400a-fg676-5 -cm area -ir off -pr off -c 100 -o xxxx.ncd xxxx.ngd xxxx.pcf
12-23-2013 11:07 PM
12-24-2013 12:06 AM
Then what is the other method of getting a chipscope cores instantiated in RTL. if I instantiate it in RTL, i should declare a module , correct ?
In the code above i have the module declared in the same file , where I instantiated. But later I have separate files ( created by coregen), but in any case, it is all same.
So please let me know your thought process.
12-24-2013 09:59 PM
01-11-2014 08:48 AM
@jkrishnanv Is this issue resolved? Feel free to post the solution for others to use is future.