UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
1,662 Views
Registered: ‎06-15-2010

Debugging PCIe with Vivado

Jump to solution

Hello!

Despite of my way to FPGA programming through self study, I rate myself as rather experienced ISE user. Using ISE+ChipScope with Spartan 6 I was able to debug my designs in chip. Now we are switching to Artix-7. I have AC-701 board for my experiments and have to use Vivado.What I managed to do is to create PCIe project, and invoke example project for it. Testing against processor showed some troubles with PCIe, so I decided to see what happens inside with very little luck. To make sure I get debug methodology, I have created simpliest design with buttons and LEDs and was able to trigger on button actions. Still I could not debug PCIe. The problem I get is ather common:

WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
INFO: [Labtools 27-1434] Device xc7a200t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'u_ila_0' at location 'uuid_23E7D65A79BC59F7BC47406C1714DFAE' from probes file, since it cannot be found on the programmed device.

Please share, what should I do to be able to se transaction interface signals like trn_rd, trn_sof.

Thanks in advance.

0 Kudos
1 Solution

Accepted Solutions
Explorer
Explorer
1,539 Views
Registered: ‎06-15-2010

Re: Debugging PCIe with Vivado

Jump to solution

Hello!

Loos like I solved the puzzle. Th background is that I had PCIe link up and even could write/read some values out of example design, but some of them were broken. So I decided to setup debug on TRN interface. As it takes time, I took the boart out of setup, and yes, debugger was complaining on no clock signal correctly, because the clock comes out of PCIe endge connctor, which was disconnected.

So when I put the board back into test setup, debugger appeared correctly. Somehow this time I had no broken data on communication. This deviates from my ChipScope experience, where scope could wait for trigger indefinitely, if clock was not running, but otherwise was functional.

Sorry for making that much traffic.

0 Kudos
7 Replies
Explorer
Explorer
1,646 Views
Registered: ‎06-15-2010

Re: Debugging PCIe with Vivado

Jump to solution
What I was doing with my memory on ChipScope of ISE, I was adding transaction interface signals like trn_rd, bar_hit and so on letting wizard decide the clock. Next I tried to drive debug hub with user_clk, but that I'm afraid is a clock which may be dropped on reset, thus not free running. Then I have no idea, how do I get truly free running clock. Should I have another DCM making always alive clock? But then TRN interface would not be driven by it, then is it okay to sample data?
Please advise.
0 Kudos
Explorer
Explorer
1,607 Views
Registered: ‎12-05-2016

Re: Debugging PCIe with Vivado

Jump to solution

hi @rrlagic ,

the clock which is used for sampling should be greater than the clock domains of the signals you are capturing. either you can select a clock with max frequency from your design or you may generate one faster clock using clocking wizard. I tried both and found working. but if you are planning to use an independant clock from DCM please give more attention because timing issues may occur.

regards,

Reshma 

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Please mark a response "Accept as solution" if a post has the solution to your issue.

If you see a particularly good and informative post, consider giving it Kudos. 

Explorer
Explorer
1,597 Views
Registered: ‎06-15-2010

Re: Debugging PCIe with Vivado

Jump to solution

Reshma,

Thank you for suggestion. I roughly understand the idea, but when it comes to practice I'm stuck. If you might have experience with PCIe, could you please point, where I could get relevant clocks?

Thanks

0 Kudos
Highlighted
Explorer
Explorer
1,576 Views
Registered: ‎12-05-2016

Re: Debugging PCIe with Vivado

Jump to solution

hi @rrlagic ,

please check the attached image. i couldnt verify it on the board. anyway you just try it.

regards,

Reshma 

trn_.JPG
0 Kudos
Contributor
Contributor
1,571 Views
Registered: ‎03-01-2018

Re: Debugging PCIe with Vivado

Jump to solution

Hi,

    If you didn't get the clk network in PCIe core,you could init a MMCM, and the input signal is pcie_user_clk, output signal could use as debug clk.

For example, pcie_user_clk is 125M, and output clk from MMCM could be 250M, and then you could use 250M as debug clk.

0 Kudos
Explorer
Explorer
1,557 Views
Registered: ‎06-15-2010

Re: Debugging PCIe with Vivado

Jump to solution

Hi, @reshmaakhil,

Thank you very much for you care. Similar to your screenshot I have added just 2 signals, Tx and Rx start of frame and made sure clock for them was similar to yours, like in the picture

 

dbgvivadopcie.png

 

 

 

 

 

 

 

 

 

 

Unfortunatelly, still I cannot debug with the message

WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
INFO: [Labtools 27-1434] Device xc7a200t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'u_ila_0' at location 'uuid_23E7D65A79BC59F7BC47406C1714DFAE' from probes file, since it cannot be found on the programmed device.
0 Kudos
Explorer
Explorer
1,540 Views
Registered: ‎06-15-2010

Re: Debugging PCIe with Vivado

Jump to solution

Hello!

Loos like I solved the puzzle. Th background is that I had PCIe link up and even could write/read some values out of example design, but some of them were broken. So I decided to setup debug on TRN interface. As it takes time, I took the boart out of setup, and yes, debugger was complaining on no clock signal correctly, because the clock comes out of PCIe endge connctor, which was disconnected.

So when I put the board back into test setup, debugger appeared correctly. Somehow this time I had no broken data on communication. This deviates from my ChipScope experience, where scope could wait for trigger indefinitely, if clock was not running, but otherwise was functional.

Sorry for making that much traffic.

0 Kudos