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Contributor
Contributor
1,144 Views
Registered: ‎04-09-2015

ERROR: [Xicom 50-38] xicom: AXI TRANSACTION TIMED OUT

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Hello everyone,

 

My specs:

ZYNQ-7 ZC706 Evaluation Board (xc7z045ffg900-2)

Vivado 2017.2

 

What I want to do:

I am using the JTAG to AXI Master v1.2 (Rev. 3) ip core to access the DDR3 Memory through a Memory Interface Generator (MIG 7 Series) v4.0 (Rev. 4) ip core within the xapp1171 example design.

 

What I have done so far:

1) Plain design

I created a block design having only the JTAG to AXI Master and the MIG 7 Series (+ an AXI SmartConnect which was added by the connection automation), like this:

00_plain_design.png

The cores/cores AXI interfaces are configured with 32 Bit address and 64 Bit data values.

Synth -> Impl -> Bitstream -> Program Device -> check!

Checked for my JTAG to AXI Master ip core being available, like this:

00_plain_design.png

 

Issued some AXI Transactions and got a result -> check!

create_hw_axi_txn rd_txn [get_hw_axis hw_axi_1] -address 00000000 -len 8 -type read
rd_txn
run_hw_axi [get_hw_axi_txns rd_txn]
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
report_hw_axi_txn [get_hw_axi_txns rd_txn]
       0  00000000 00000000 
       8  00000000 00000000 
      10  00000000 00000000 
      18  00000000 00000000 
      20  00000000 00000000 
      28  00000000 00000000 
      30  00000000 00000000 
      38  00000000 00000000 

2) I added the JTAG to AXI Master core to the xapp1171 example design and made sure that all the AXI interfaces are using the 32 Bit address/64 Bit data values, like this:

01_xapp1171_design.png

01_xapp1171_design_ae.png

Synth -> Impl -> Bitstream -> Program Device -> check!

Checked for my JTAG to AXI Master ip core being available, like this:

00_plain_design.png

 

Issued some AXI Transactions and got the following result:

01_xapp1171_design_waiting.png

create_hw_axi_txn rd_txn [get_hw_axis hw_axi_1] -address 00000000 -len 8 -type read
rd_txn
run_hw_axi [get_hw_axi_txns rd_txn]
ERROR: [Xicom 50-38] xicom: AXI TRANSACTION TIMED OUT
INFO: [Labtoolstcl 44-481] READ DATA is: 
run_hw_axi: Time (s): cpu = 00:00:01 ; elapsed = 00:00:26 . Memory (MB): peak = 1973.410 ; gain = 0.000
ERROR: [Common 17-39] 'run_hw_axi' failed due to earlier errors.
report_hw_axi_txn [get_hw_axi_txns rd_txn]
       0  00000000 00000000 
       8  00000000 00000000 
      10  00000000 00000000 
      18  00000000 00000000 
      20  00000000 00000000 
      28  00000000 00000000 
      30  00000000 00000000 
      38  00000000 00000000 

I know, no real need for the "report_hw_axi_txn [get_hw_axi_txns rd_txn]" at the end there, just did it for the sake of completeness :)

 

My question:

Do I have some missunderstanding within the design somewhere?

I know that the SmartConnect is kinda redundant and one can just use one AXI Interconnect to connect all of them, but in the end that shouldn't really matter, does it?

Are there maybe any missunderstandings within the Address Editor from my side?

 

Appreciate any help I can get :)

 

EDIT: For some reason my post got deleted/was never shown...

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Contributor
Contributor
1,671 Views
Registered: ‎04-09-2015

Re: ERROR: [Xicom 50-38] xicom: AXI TRANSACTION TIMED OUT

Jump to solution

Seems to work when connecting the JTAG to AXI Master core with a SmartConnect to the main AXI Interconnect, like this:

 

working.pngworking00.png

 

Although I only receive zeros, which seems kinda strange... but hey, at least I get some response from the JTAG to AXI Master core.

1 Reply
Highlighted
Contributor
Contributor
1,672 Views
Registered: ‎04-09-2015

Re: ERROR: [Xicom 50-38] xicom: AXI TRANSACTION TIMED OUT

Jump to solution

Seems to work when connecting the JTAG to AXI Master core with a SmartConnect to the main AXI Interconnect, like this:

 

working.pngworking00.png

 

Although I only receive zeros, which seems kinda strange... but hey, at least I get some response from the JTAG to AXI Master core.