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Visitor racaboodeo
Visitor
6,258 Views
Registered: ‎10-26-2012

FIFO Dropping Bytes

I'm running ISE 13.4 and using Fifo Generator 8.4 to generate a fifo with independent clocks in block RAM onto a Spartan 3AN XCS700an.  The FIFO has a write width of 8 bits at a depth fo 128 and a read width of 32 bits.  I'm using it to buffer parallel data from a camera into a RAM chip at 133MHz.  I've been using a similar design that had a write width of 16 for a couple of years without issue.  I've now noticed that ocasionally entier 32bit words are lost somewhere between din and dout.  Below is an example of what I'm seeing.  

 

IN :00  01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

 

OUT: 00010203 04050607 0C0D0E0F 

 

Where the entire group 08090A0B is just missing.  I can watch this happen in chipscope with an active write clock and write enable.  I happens about once every 170 reads.  Any suggestions?

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Xilinx Employee
Xilinx Employee
6,247 Views
Registered: ‎07-11-2011

Re: FIFO Dropping Bytes

Hi,

 

133Mhz is read frequency? What is write frequency?

What do you mean by dropping bytes?

When you isued address and read enable correcponding to the data  08090A0B dont you see any data chnage on the read data bus? or previous data is latched on it ? or what excatly do you see on read bus for that location?

Did you check  if your deisgn has timing issues and read address is proper?

Does it occur only on board or can it be replicated in simulation as well?

Is this issue seen with simple example design or in your over all design?

Would it be possible for you to capture write, read timing waveforms for the failing address and share us?

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