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Visitor alessandro91
Visitor
9,384 Views
Registered: ‎07-18-2016

Hardware Manager finds no debug cores

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Hello,

I'm working on a Zybo board by Digilent and I want to use the only FPGA part of the zynq7000.

I instantiate ILA (set up the debug after the synthesis), selecting some signals and using only clocks generated from a MMCM starting from the free running clock on the pin L16 (I also tried to use the clock after the IBUF followed by BUFG). 

I succeed in generating the bitstream, but when I open target in the hardware manager the message "There are no debug cores" appears and I cannot use ILA to debug my system.

When I run 'report_debug_core' in the Tcl console I get the following output:

 


Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
| Date : Mon Jul 18 16:29:20 2016
| Host : archimede17 running 64-bit Fedora release 15 (Lovelock)
| Design : Main
| Device : xc7z010clg400-1
| Speed File : -1
------------------------------------------------------------------------------------

Debug Core Information

Table of Contents
-----------------
1. Debug Cores
1.1 dbg_hub: (labtools_xsdbm_v1, black box, inserted)
1.2 u_ila_0: (labtools_ila_v6, black box, inserted)
1.3 u_ila_1: (labtools_ila_v6, black box, inserted)

1. Debug Cores
--------------

1.1 dbg_hub: (labtools_xsdbm_v1, black box, inserted)
-----------------------------------------------------

Parameter Data for Debug Core "dbg_hub"
+----------------------+-----------+
| Parameter | Value |
+----------------------+-----------+
| C_CLK_INPUT_FREQ_HZ | 300000000 |
+----------------------+-----------+
| C_ENABLE_CLK_DIVIDER | false |
+----------------------+-----------+
| C_USER_SCAN_CHAIN | 1 |
+----------------------+-----------+


Channel Data for Debug Core "dbg_hub"
+---------------+---------+---------------+------------------+----------+------------+------------+
| Port Name | Port | Port Spec | Channel Name | Net Type | MARK_DEBUG | Net Name |
| | Type | | | | | |
+---------------+---------+---------------+------------------+----------+------------+------------+
| clk | input | clk | clk[0] | signal | false | CLK_IN1 |
+---------------+---------+---------------+------------------+----------+------------+------------+


Peripherals Connected to Debug Hub 'dbg_hub' (2 Peripherals):
+-------+----------+---------------+
| Index | Type | Instance Name |
+-------+----------+---------------+
| 0 | ila_v6_1 | u_ila_0 |
+-------+----------+---------------+
| 1 | ila_v6_1 | u_ila_1 |
+-------+----------+---------------+


1.2 u_ila_0: (labtools_ila_v6, black box, inserted)
---------------------------------------------------

Parameter Data for Debug Core "u_ila_0"
+-----------------------+-------+
| Parameter | Value |
+-----------------------+-------+
| ALL_PROBE_SAME_MU | true |
+-----------------------+-------+
| ALL_PROBE_SAME_MU_CNT | 4 |
+-----------------------+-------+
| C_ADV_TRIGGER | true |
+-----------------------+-------+
| C_DATA_DEPTH | 1024 |
+-----------------------+-------+
| C_EN_STRG_QUAL | true |
+-----------------------+-------+
| C_INPUT_PIPE_STAGES | 0 |
+-----------------------+-------+
| C_TRIGIN_EN | false |
+-----------------------+-------+
| C_TRIGOUT_EN | false |
+-----------------------+-------+


Channel Data for Debug Core "u_ila_0"
+---------------+---------+---------------+--------------------------------+------------------+----------+------------+--------------+
| Port Name | Port | Port Spec | Parameters | Channel Name | Net Type | MARK_DEBUG | Net Name |
| | Type | | | | | | |
+---------------+---------+---------------+--------------------------------+------------------+----------+------------+--------------+
| clk | input | clk | | clk[0] | signal | false | clk_sonda |
+---------------+---------+---------------+--------------------------------+------------------+----------+------------+--------------+
| probe0 | input | probe | PROBE_TYPE=DATA_AND_TRIGGER | probe0[0] | signal | false | frame1 |
+---------------+---------+---------------+--------------------------------+------------------+----------+------------+--------------+


1.3 u_ila_1: (labtools_ila_v6, black box, inserted)
---------------------------------------------------

Parameter Data for Debug Core "u_ila_1"
+-----------------------+-------+
| Parameter | Value |
+-----------------------+-------+
| ALL_PROBE_SAME_MU | true |
+-----------------------+-------+
| ALL_PROBE_SAME_MU_CNT | 4 |
+-----------------------+-------+
| C_ADV_TRIGGER | true |
+-----------------------+-------+
| C_DATA_DEPTH | 1024 |
+-----------------------+-------+
| C_EN_STRG_QUAL | true |
+-----------------------+-------+
| C_INPUT_PIPE_STAGES | 0 |
+-----------------------+-------+
| C_TRIGIN_EN | false |
+-----------------------+-------+
| C_TRIGOUT_EN | false |
+-----------------------+-------+


Channel Data for Debug Core "u_ila_1"
+---------------+---------+---------------+--------------------------------+------------------+----------+------------+------------+
| Port Name | Port | Port Spec | Parameters | Channel Name | Net Type | MARK_DEBUG | Net Name |
| | Type | | | | | | |
+---------------+---------+---------------+--------------------------------+------------------+----------+------------+------------+
| clk | input | clk | | clk[0] | signal | false | CLK_IN1 |
+---------------+---------+---------------+--------------------------------+------------------+----------+------------+------------+
| probe0 | input | probe | PROBE_TYPE=DATA_AND_TRIGGER | probe0[0] | signal | false | gate |
+---------------+---------+---------------+--------------------------------+------------------+----------+------------+------------+


report_debug_core: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.08 . Memory (MB): peak = 7516.145 ; gain = 0.000 ; free physical = 2804 ; free virtual = 22315

 

Am I making any mistake? I really don't know how to proceed

 

PS: I attach the constraint file .xdc

 

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1 Solution

Accepted Solutions
Visitor alessandro91
Visitor
16,497 Views
Registered: ‎07-18-2016

Re: Hardware Manager finds no debug cores

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Thank you for your quick answer. 
I tried what you suggested, but I couldn't solve the problem. Then I generated a new project, identical to the previous one and I introduced a VIO that takes the same inputs of the ILA core. Now everything is working.

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5 Replies
Xilinx Employee
Xilinx Employee
9,328 Views
Registered: ‎02-14-2014

Re: Hardware Manager finds no debug cores

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Hello @alessandro91,

 

Can you follow below suggestions and update the results -

 

1. After configuring the device, right click and select 'Refresh Device'. This re-scans the FPGA device and refreshes the Hardware window.

2. If you still do not see the ILA core after programming and/or refreshing the FPGA device, cross-verify that device was programmed with the appropriate .bit file

3. Make sure that implemented design contains an ILA core. Also, check to make sure the appropriate .ltx probes file that matches the .bit file is associated with the device.

Regards,
Ashish
----------------------------------------------------------------------------------------------
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Moderator
Moderator
9,324 Views
Registered: ‎07-01-2015

Re: Hardware Manager finds no debug cores

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Hi @alessandro91,

 

Can you please check if the clock of the dbg_hub is connected after BUFG or not?

Also tie the reset signal of MMCM to 0 if not connected.

Thanks,
Arpan
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Visitor alessandro91
Visitor
16,498 Views
Registered: ‎07-18-2016

Re: Hardware Manager finds no debug cores

Jump to solution

Thank you for your quick answer. 
I tried what you suggested, but I couldn't solve the problem. Then I generated a new project, identical to the previous one and I introduced a VIO that takes the same inputs of the ILA core. Now everything is working.

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Moderator
Moderator
9,268 Views
Registered: ‎07-01-2015

Re: Hardware Manager finds no debug cores

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Hi @alessandro91,

 

Glad to know your issue got resolved.

Did you see any difference in schematics of passing and failing design?

Please close this thread by marking your answer as "Accept as solution".

Thanks,
Arpan
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Newbie saunak28
Newbie
2,588 Views
Registered: ‎06-27-2018

Re: Hardware Manager finds no debug cores

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What is VIO?

 

How you have solved the problem kindly explain in briefly

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