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Visitor milagorobets
Visitor
9,725 Views
Registered: ‎07-27-2014

ILA Debug Core Clock problem ("Failed to get a response from the Debug Core Hub")

I am trying to debug my IP design using ChipScope.

 

The S_AXI_ACLK pin of my IP is connected to FCLK_CLK0, and set to 100MHz. 

 

I have tried setting up the debugging core with FCLK_CLK0 as the clock domain, but that produces an error:

ERROR: [Labtools 27-147] vcse_server: XSDB Master timed out.
ERROR: [Labtools 27-1437] Failed to get a response from the Debug Core Hub on device xc7z020_1 (JTAG device index = 1), in user chain = 1.
Resolution:
1) Verify that the clock signal connected to the debug core is clean and free-running.
2) Verify that the clock connected to the debug core meets all timing constraints.

 

I then switched the debugging core to use FCLK_CLK1 as the clock domain, but that produces the same error. I have set the frequency of CLK1 to 200MHz, but that doesn't change anything. 

 

The FCLK_CLK0 signal isn't connected to anything except S_AXI_ACLK on my design. Any ideas for what I can do to get it to work?

 

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2 Replies
Xilinx Employee
Xilinx Employee
9,704 Views
Registered: ‎07-21-2014

Re: ILA Debug Core Clock problem ("Failed to get a response from the Debug Core Hub")

hello,

 

please try using following commands.

 

set DEBUG_HUB_CLK_PIN [get_pins dbg_hub/XSDB_CLK_I]
disconnect_net -net [get_nets -of $DEBUG_HUB_CLK_PIN] -objects $DEBUG_HUB_CLK_PIN
connect_net -net [get_nets <continously running clock net name>] -objects $DEBUG_HUB_CLK_PIN

 

hope this helps

 

thanks,

Shreyas

 

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Xilinx Employee
Xilinx Employee
9,691 Views
Registered: ‎10-24-2013

Re: ILA Debug Core Clock problem ("Failed to get a response from the Debug Core Hub")

Hi,
Check if you have any timing violations in your design.
Thanks,Vijay
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