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Participant cesar182
Participant
146 Views
Registered: ‎08-07-2018

Implement VHDL code to debug in Chipscope

Greetings ... I tell you that I am new to Vivado, and I would like someone to help me find information to implement VHDL code that I can use to debug through Chipscope. Also comment that I am using Vivado 2017.3, any help is welcome, thanks in advance.

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3 Replies
Moderator
Moderator
110 Views
Registered: ‎02-09-2017

Re: Implement VHDL code to debug in Chipscope

Hi @cesar182,

There are two main ways of implementing the ILA in a design, VHDL/Verilog instantiation, or Netlist Inserting (aka Setup Debug flow).

Please refer to the document Vivado Design Suite Tutorial - Programming and Debugging - UG936, Lab 1, Lab 2, and Lab 5, which contains a tutorial for each of those methods.

The document Vivado Design Suite User Guide - Programming and Debugging - UG908, Chapter 10 and Chapter 11, also explains the flow and differences between the two methods.

After you review it, please let us know if you have any question or find any issue when implementing it.

Thanks,

Andre Guerrero

Product Applications Engineer

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Participant cesar182
Participant
94 Views
Registered: ‎08-07-2018

Re: Implement VHDL code to debug in Chipscope

Thanks for answering @anunesgu, I told you that I tried to implement the lab1 example, but I can not correctly generate the Bitstream because of the error shown in the attached image.
I tried to replace each of the xci files, but it does not work for me and I still get the same error.
What would be the problem in this case? Thanks in advance.

errGenBitstream.PNG
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Moderator
Moderator
25 Views
Registered: ‎02-09-2017

Re: Implement VHDL code to debug in Chipscope

Hi @cesar182,

 

It looks like the SINEGEN modules that you imported when creating the project (sinegen high, medium, and low) are not being recognized by Vivado. Most likely, this is because the Vivado version that you are using is newer that the version used to created those files. When this happens, the IPs get locked and you can't use them until you upgrade them to a compatible version.

Please expand the U_SINEGEN under Sources and verify if all the three XCI files are there and if they have a red lock icon as in the image below:

Sources_IP_locked_UG936.JPG

In the top tools bar, click on Reports -> Report IP Status. You should see a window as the one below:

Report_IP_Status_UG936.JPG

You can see that indeed those IPs need to be upgraded. Make sure that all IPs are selected and click on Upgrade Selected. After a little while, a pop-up should appear, saying that they were successfully upgraded.

Once you click OK, another pop-up should appear, asking if you want to generate the output products. Click on Generate.

generate_output_products_UG936.JPG

If this window is not shown, manually right-click on each of the three IPs (under the Sources tab) and select the Generate Output Products option.

Once this is done, you should be able to regenerate the Synthesis, insert the ILA, and generate the Implementation with no errors.

I just did all this process right now and confirm that it worked for me.

Please try these steps and let me know if you encounter any issue.

Thanks,

Andre Guerrero

Product Applications Engineer

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