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3,103 Views
Registered: ‎05-13-2016

Is there a way to name probes or rename signals when running setup debug

In setting up a debug run fro Hardware Analyzer, there does not seem to be a way to name the ports.  It is a pain in the butt to open the analyzer and try to figure out what signal is which.  I know that in the viewer you can assign signals a short name, but by then its to late.  You cannot click on a signal in the analyzer and get the schematic view to see where it came from.  It would be nice to set this up when setting up the debugger, while you have the information available.  Am I missing something here?

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4 Replies
Scholar markcurry
Scholar
3,023 Views
Registered: ‎09-16-2009

Re: Is there a way to name probes or rename signals when running setup debug

 

Asked, and ignored at least a few years ago: https://forums.xilinx.com/t5/Design-Tools-Others/Vivado-Analyzer-names-and-ltx-files-and-mark-debug-attributes/td-p/664890

 

Every few months another user ask for this, and is ignored.  Vivado Analyzer seems to be at the bottom of the list for fixes.  It's still not up the capabilities of the product it replaced (Chipscope).  But I guess looking prettier (but less capable) is more important.

 

I sometimes wish Xilinx would just publish some sort of API for the debugger so we could just write / tie-in our own waveform display and trigger control.  No actually I don't - I don't have time for that.  I just want it to work, a bit better than it currently does. 

 

Actually if I could just run the old Chipscope Analyzer with the current FPGAs I'd be just as happy.  I was doing that for a long time (unsupported of course) in Kintex designs.  Just used the same-old ICON/ILA edf files I always used (generated circa ISE 13.3) with the latest and greatest FPGAs.  Worked fine until the JTAG enumeration stop working on the lastest FPGAs... Grrrr.

 

Regards,

 

Mark

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2,919 Views
Registered: ‎05-13-2016

Re: Is there a way to name probes or rename signals when running setup debug

Is there a way to contact the moderator....

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Moderator
Moderator
2,903 Views
Registered: ‎07-01-2015

Re: Is there a way to name probes or rename signals when running setup debug

Hi paul.gigliotti@coachcomm.com,

 

You can go for user defined probe. Please go through page-137 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug908-vivado-programming-debugging.pdf

Thanks,
Arpan
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2,889 Views
Registered: ‎05-13-2016

Re: Is there a way to name probes or rename signals when running setup debug

This is nice but, it is not what I am after, or what we need.  When I first set up debug, after synthesis, but before implementation, I want to name the probes as I add them into the design, so that when hardware manager comes up, I will easily tell what I am looking at.

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