01-22-2015 03:37 PM
I'm attempting to integrate the JTAG to AXI master into a design and the build is failing with the following:
ERROR: [Chipscope 16-213] The debug port 'dbg_hub/clk' has 1 unconnected channels (bits). This will cause errors during implementation.
Looking at the closest design checkpoint I can see the JTAG master and the dbg_hub in the netlist. Of note is that the dbg_hub is not a submodule of the JTAG master so I don't know how the tool knows how to hook that up. If I have Vivado create a schematic of the dbg_hub then it shows an unconnected clock. The JTAG master itself is connected correctly.
We have a "unique" build environment that I thought might be getting in the way but I am able to build a simple design with just the JTAG master and a BRAM attached and it completes. In my design the JTAG master is driving an AXI crossbar that distributes the bus to various register blocks throughout the design. I don't see anything in the log about the dbg_hub until the error occurs which stops the build.
Any ideas about what could be keeping the tool from hooking this up would be appreciated.
01-22-2015 11:01 PM
01-23-2015 03:52 PM
Our build environment makes it difficult to share. The design has an AXI-Lite control bus that typically starts with a SPI controller. A crossbar is used to distribute this throughout the design. I have a parameter that I can pass into the build to replace the SPI controller with the JTAG master using the following instantiation:
jtag_master jtag_master (
.aclk (sys_clk ),
.aresetn (~sys_reset ),
.m_axi_awaddr (axil_spi_awaddr ),
.m_axi_awprot (axil_spi_awprot ),
.m_axi_awvalid (axil_spi_awvalid ),
.m_axi_awready (axil_spi_awready ),
.m_axi_wdata (axil_spi_wdata ),
.m_axi_wstrb (axil_spi_wstrb ),
.m_axi_wvalid (axil_spi_wvalid ),
.m_axi_wready (axil_spi_wready ),
.m_axi_bresp (axil_spi_bresp ),
.m_axi_bvalid (axil_spi_bvalid ),
.m_axi_bready (axil_spi_bready ),
.m_axi_araddr (axil_spi_araddr ),
.m_axi_arprot (axil_spi_arprot ),
.m_axi_arvalid (axil_spi_arvalid ),
.m_axi_arready (axil_spi_arready ),
.m_axi_rdata (axil_spi_rdata ),
.m_axi_rresp (axil_spi_rresp ),
.m_axi_rvalid (axil_spi_rvalid ),
.m_axi_rready (axil_spi_rready )
There isn't much to the JTAG master. It's setup for AXI4LITE and the queues are set to 1. There isn't much more to it than that.
I'm going to try some other experiments to see if I can provide more information...
01-23-2015 05:29 PM
01-26-2015 12:03 PM
I don't. This is a new design and it's not very big. Adding this control port is the first "debug" effort we've attempted so far so there are no lingering debug items anywhere else in the system.
I was able to take the example project and build it without errors. (JTAG master to BRAM.) I moved these two blocks into our design as a unit issolated from everything else to see if it had to do with what was on the other end of the AXI bus. However it produced the same error.
What clock is this and how do the tools know what to hook it up to normally?