09-26-2013 04:44 AM
I am generating bit file for Xilinx FPGA(Virtex 6,xc6vlx240t-2-ff1759) through Xilinx ISE version 14.2 on Linux 64-bit computer.
In our project, Xilinx FPGA(Virtex 6,xc6vlx240t-2-ff1759) board is connected to PCI Express slot of the computer's mother board.
I want to capture some signals in chipscope, so I have made cdc file for chipscope. And then I am generating bit file.After downloading bit and cdc file into FPGA, Linux operating system is crashed.
But if I add some more signals(Original signals are not removed) into cdc file and then again genearting bit file, after downloading bit and cdc file into FPGA, Linux operating system is not crashed. It works fine.
If I generate bit file after removing cdc file from project(Without any chipscope signals), at that time, also Linux operating system is crashed.
Please give me some solution for this problem.
09-30-2013 11:48 PM
This looks like a strange behavior. Does it happen with any design or only your specific design. I guess there might be some paramenters which the OS is unable to handle and also some processor compatibility problem. Can you try inserting the FPGA into a different processor or a different machine and check if the problem repeats.
Better try the TRD's and PCIE reference design which we have locally for various boards, in case you are using our evaluation board.
10-07-2013 08:48 PM
Any update on this issue? Were you able to resolve this?