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Observer drewboud
Observer
255 Views
Registered: ‎10-30-2014

MPSoC ZU19EG SGMII IBERT 2018.2

It was desired to use the PS-GTR IBERT feature to ensure physical operation of a custom board with no PHY, GTR's looped directly.  An FSBL was generated with GEM0 set to SGMII on PS-GTR lane 0.  In Vivado HW Manager the FSBL was loaded and IBERT started.  PLL's showed lock but SGMII status was no link.  After probing a few GEM0 registers it was determined a few other bits needed to be set to ensure link.  The network_config register (0xFF0B0004) was written with 0x08280C00 to set the sgmii_mode_enable, pcs_select, and gigabit_mode_enable.  Once these bits were set IBERT reported Link Up.  I am posting this in case anyone else hits this issue. 

Thank you.     

1 Reply
Moderator
Moderator
181 Views
Registered: ‎02-09-2017

Re: MPSoC ZU19EG SGMII IBERT 2018.2

Hi @drewboud,


Thank you for posting about this issue and the solution!

I'll go ahead and investigated it and possibly create an AR to further facilitate the finding of this resolution.

 

Thanks,

 

Andre Guerrero

Product Applications Engineer

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