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Manual Logic Analyzer implementation and Linux context

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Scholar
Posts: 352
Registered: ‎03-27-2014

Manual Logic Analyzer implementation and Linux context

I just figured how to do this so I might aswell share it with you guys.

 

Manual routing of the logic analyzer is the only option if you are trying to trigger on signals that are only here for debugging purposes: they're not being used in the design, not routed, they cannot be 'marked as debug'.

 

Add the ILA core to the block design and customize it accordingly (number of probes, probes width, buffer depth, add trigger In/Out ports[important]).

ila_0.png

 

 

In the customize interface of the Zynq IP, check PS/PL Cross trigger interface in the PS-PL configuration tab.

ila_1.png

 

Connect TriggerIn(Zynq) to TriggerOut(ILA) and TriggerOut(Zynq) to TriggerIn(ILA).

Connect your debug signals to the probes inputs.

Generate the bitstream.

 

Move to Linux on the Zynq CPU:

 

cat bitstream_with_ILA.bit > /dev/xdevcfg

Now in Vivado: open hardware/JTAG interface => the probes are detected.

 

Trigger the debug bit from your Linux application..

./main

-> best way to debug kernel/FPGA interfaces.

G.W.,
NIST - Time Frequency metrology
Contributor
Posts: 43
Registered: ‎05-27-2015

Re: Manual Logic Analyzer implementation and Linux context

Hi

Thank you very much for sharing this. I have a question though. The last step is to enable the debug bit. What do you mean by this ?

Does it mean that I activate the CTI enable bit in CTL and ACK register or it has nothing to do with these registers Thank you very much in advance.

Best Regards

MAW

Scholar
Posts: 352
Registered: ‎03-27-2014

Re: Manual Logic Analyzer implementation and Linux context


abdulparis wrote:

Hi

Thank you very much for sharing this. I have a question though. The last step is to enable the debug bit. What do you mean by this ?


well I agree this not clear at all I should rephrase that thing,

I just meant I had some sort of C program that was triggering something in the FPGA, and I used the ILA to monitor that bit,

the flag originally comes from the ARM CPU and is passed to the FPGA

G.W.,
NIST - Time Frequency metrology
Contributor
Posts: 43
Registered: ‎05-27-2015

Re: Manual Logic Analyzer implementation and Linux context

Thank you very much. That's what I was thinking and I did it but I was having a kernel panic that's why I wanted to make sure.

Did you get any kernel panic on yout Linux side ?

Best Regards,
MAW

 

Scholar
Posts: 352
Registered: ‎03-27-2014

Re: Manual Logic Analyzer implementation and Linux context


abdulparis wrote:

Thank you very much. That's what I was thinking and I did it but I was having a kernel panic that's why I wanted to make sure.

Did you get any kernel panic on yout Linux side ?


I don't know what you are doing but you will get a kernel panic anytime you try to access a non valid memory region for instance (your memory mapped FPGA core has to be properly mapped)

G.W.,
NIST - Time Frequency metrology