UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
207 Views
Registered: ‎12-08-2007

Message: No debug cores, when trying to use ILA

I am learning to use the ILA.

I create a half-adder, create an .xdc file (for Basys3 board).

After adding ILA IP from the catalog, I insert in VHDL the ILA component. Here is the VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main is
    Port ( clk100mhz: in std_logic; -- for the ILA
    
           x : in STD_LOGIC;
           y : in STD_LOGIC;
           s : buffer  STD_LOGIC; -- we need buffer in order to read it for ILA
           c : buffer  STD_LOGIC);
end main;

architecture Behavioral of main is

component ila_0
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
    probe1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END component;

begin

MYILA: ila_0 PORT map (clk => clk100mhz, probe0(1) => x, probe0(0) => y, probe1(1) => s, probe1(0) =>c);


s <= x xor y;
c <= x and y;

end Behavioral;

I run synthesis. I see two critical warnings in the synthesized design, which pertain to the clock100Mhz lines in the .xdc. (see enclosed, ). I am not sure what the warnings are because  all other lines in .xdc that regard the other nets do not give a warning.

Then, I choose "Set Up Debug" and I have 4 nets to debug. (see enclosed).

I run Implementation fine. I add in the bitstream settings a file .TCL which contains the following code:

set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

because I have most of the pins of the FPGA  are not used.

I then generate bitstream. I program the .bit to the FPGA.

I open the Hardware manager but I see a message that there are no debug cores. (see enclosed). 

So I cannot start the Logic Analyzer.

The design itself is programmed into the FPGA and I can validate the Half-Adder  manually (using Switches and Leds).

But I would like to run the Logic Analyzer.

 

Any advise?

 

Screen Shot 2018-12-31 at 13.15.06.png
Screen Shot 2018-12-31 at 11.54.50.png
Screen Shot 2018-12-31 at 13.21.15.png
Capture8.PNG
Screen Shot 2018-12-31 at 13.31.09.png
0 Kudos
5 Replies
Moderator
Moderator
175 Views
Registered: ‎02-09-2017

Re: Message: No debug cores, when trying to use ILA

Hi @dag1,

To make things easier a bit, instead of instantiating the ILA in VHDL as you did, lets try to use the Set Up Debug Flow instead.

Just for a better understanding of the process, there are two ways of inserting the ILA into a Design: \

  • Inserting it right into the VHDL/Verilog code (just as you did);
  • Just do your main logic in VHDL/Verilog and do not insert any ILA until the Synthesis Process is done, at which point you will click on the Setup Debug button and do it through the GUI.

The Setup Debug method is the easier and faster way to do it. I'd recommend using the VHDL/Verilog Instantiation method just in more advanced cases, where the Setup Debug is not capable of doing it. You should avoid using both methods in the same design.

So to do so, you can remove the ILA IP you created from the catalog and remove any evidence of the ILA from your VHDL code. Carry on with the synthesis process and once you're done, please follow the Setup Debug Flow, as in the document Vivado Programming and Debugging - UG908, pg. 118 to 121.

Please reply back once you've done this process and let us know if you're still seeing issues, if there's any new errors/warnings, etc.

In addition, the "set_property" warning you are seeing is most likely because the object name doesn't exist yet (maybe it's a derived clock, which Vivado only knows it exists after the synthesis is done). Since you said that the logic itself is working, I would not worry about it for now, but we can look at it later too.

Thanks,

Andre Guerrero

Product Applications Engineer

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Moderator
Moderator
173 Views
Registered: ‎02-09-2017

Re: Message: No debug cores, when trying to use ILA

Just to let you know, I noticed that there were two posts of yours with the same question, so I deleted one just so we concentrate our efforts on this one.

Thanks!

Andre Guerrero

Product Applications Engineer

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Explorer
Explorer
116 Views
Registered: ‎12-08-2007

Re: Message: No debug cores, when trying to use ILA

Hi

 

I follow our suggestion and I start a new project.

HDL only has the Half Adder code. 

The new project has no ILA IP as you requested.

I run synthesis.

I do 

set up debug:

I open the NetList and I drag the following 4 signals into the "Nets to Debug" window:

c_OBUF

s_OBUF

x_IBUF

y_IBUF

I then see "Clock Domain" undefined for all four.

I Right Click,  Select Clock Domain, but get message that no clock domain found. I try to choose ALL_CLOCK, but get message "Nothing found for: ALL_CLOCK".

I assume that there needs to be some clock for sampling (although I have not yet at this point added ILA from the catalog) so I have added an input signal in the entity (in VHDL) which is CLK100MHZ.

The .xlc constraint file has all four signals, and the signal called CLK100MHZ (with the pin W5 on the Basys3 board). 

I can see it in the Schematic (unconnected) after synthesis. But still, I am unable to choose this clock for the purpose of Clock Domain.

So I am stuck here. (I followed p. 118 - 119 up to this point). So no ILA IP has been inserted .

 

What should I do to resolve this?

 

0 Kudos
Moderator
Moderator
92 Views
Registered: ‎02-09-2017

Re: Message: No debug cores, when trying to use ILA

Hi @dag1,

 

It looks like your clock is not connected to anything because your buffers are declared as asynchronous (they don't really depend of any clock). It's a good practice to always have these type of registers in sync with a clock. Id addition, the ILA expects to use the same clock that is being used in the logic, so since you don't have any clock being used, it can't find any either.

I suggest you modify your VHDL to have the registers be synchronized with the input clock. You should be able to just modify your code to have something like:

 

process (clk100mhz)
begin
    if rising_edge(clk100mhz) then
        s <= x xor y;
        c <= x and y;
    end if;
end process;

At that point, once you synthesize it, since now the update of the s and c outputs depend of the clk100mhz rising edge, Vivado will make that clock available for you in the Setup Debug window and you should be able to finalize the ILA insertion.

Thanks,

 

Andre Guerrero

Product Applications Engineer

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Explorer
Explorer
68 Views
Registered: ‎12-08-2007

Re: Message: No debug cores, when trying to use ILA

As you know, a Half Adder is a combinational circuit, not a sequential one (no clock).

I added the clock (and not connected it) because that would change the behavior of the Half Adder.

Before I try your suggestion, I want to understand something basic about the Vivado: Combinational circuits cannot be debugged by the ILA IP ?

 

 

0 Kudos