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Newbie sworld
Newbie
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Registered: ‎10-30-2014

RAM256X1S address port problem in Vivado

There seems to be a problem with using the RAM256X1S address ports in EDIF cores in Vivado. We have been using eight lines for the address labelled A0 to A7, consistent with how previous address inputs have been used in RAM primitives in Xilinx. This primitive works fine in ISE but gives the following error message in Vivado 2014.2 using a Zync part. The problem also occurs in version 2014.3.

[Netlist 29-181] Cell 'RAM256X1S' defined in file 'play.edn' has pin 'A0' which is not valid on primitive 'RAM256X1S'.  Instance 'U_O/U_O' will be treated as a black box, not an architecture primitive ["C:/play/play.edn":75]

All the other Xilinx primitives in our core that have lines for their address work fine in Vivado. We can fix the problem by changing the address lines in the primitive to a bus A[7:0], but this is not an easy change to make in our EDIF cores.

Any chance Xilinx can fix this problem in their next version of Vivado?

Attached is a top level VHDL file and example EDIF core with the RAM256X1S primitive.

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