07-02-2019 04:56 AM
I would like to debug with chipscope in a zynq fpga, remotely over ethernet. The zynq arm is running linux.
For this purpose I added the Debug Bridge IP in 'From AXI to BSCAN' mode. I also added several signals in the 'Set up debug' window of Vivado, for which I would like to use chipscope. In my implemented design I see three ILA cores, which are connected to a debug hub, which is connected to the debug bridge.
I compiled and run the following program inside linux on the arm core: https://github.com/Xilinx/XilinxVirtualCable/blob/master/XAPP1251/src/xvcServer.c#L301
When I connect to the XVC server from the Vivado 2018.2 hardware manager, I do see a device called 'debug_bridge_0', however I do not see the actual fpga or xadc. Vivado mentions that the debug_bridge_0 is not programmed. What can be the problem?
07-08-2019 03:32 PM
Are you using a Zynq-7000 or Zynq US+ device? Just to mention, for Zynq US+ devices, the process described in XAPP1251 might not work, and there is a more up-to-date guide in the blog post Designing an XVC project for Remote Debugging of Zynq UltraScale+ devices.
Using XVC, you will not see the device or XADC. You should see something similar to the image below:
Since you are seeing the debug bridge, I suspect that the XVC connection is correct and just the ILA is actually not being connected to the debug bridge.
So I can udnderstand better your design flow, did you create the whole design using the Block Diagram (IPI) but latter you added the ILAs using the Setup Debug wizard? I suspect that in this case the connections between ILA and Debug Bridge will not be made correctly. Could you try to add the ILAs also in the IPI and try again?
07-08-2019 11:10 PM
Hello @anunesgu ,
I'm using a zynq device with Vivado 2018.2. I'm using a flow without IPI, so plain VHDL with several Xilinx IPs instantiated.
I think I know what caused the issue. I setup chipscope by opening the synthesized design and using the 'Setup debug' menu. After that I implemented the design and created bitstream. However, I did not have access to the jtag port, so then I added a Debug bridge IP and made a new bitstream. This did not gave any critical warnings or errors. Also in the implemented design, the debug bridge was connected to the debug hub, which was connected to the ILA cores, so it all looked fine. However, no ILA cores were visible when using chipscope with XVC.
When I tried it on a new design I first added the debug bridge and then tried to click 'Setup debug'. It then said that setup debug is not supported when there is a debug bridge in the design. When I manually added an ILA IP it worked and I saw the ILA with remote chipscope with XVC.
I still don't really understand why it did not work in the first situation, as I saw in the implemented design that the debug bridge was properly connected to the debug hub, which was connected to the ILA cores.
Are there any plans to support the Debug Bridge in combination with 'Setup debug' in future versions of Vivado? I think that would be really useful. Manually setting up the ILA cores is much more work.