UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor derrickg
Visitor
403 Views
Registered: ‎05-04-2016

Using XVC and Debug bridge to chipscope a local Zynq design

I have found resources that will let me:

  1. Turn a microzed into an expensive JTAG cable. (xapp1251)
  2. Use PCIe to debug a locally connected FPGA. (video)

What I haven't found is a driver/program that will let me run xvcserver on a Zynq to debug a design on the same chip.  Does such a thing exist?  Or do I have to modify one of the previously mentioned examples to implement this myself?  We actually did try to adapt xapp1251 to allow the ARM to drive JTAG for the FPGA, but it locks at some point so I think that is a deadend. 

This seems like an obvious application, so I am perplexed by the lack of an examples.

0 Kudos
5 Replies
Moderator
Moderator
357 Views
Registered: ‎02-09-2017

Re: Using XVC and Debug bridge to chipscope a local Zynq design

Hi @derrickg,

 

That's a great question. We are actually working on a new XAPP (similar to the XAPP1251) that will use a MPSoC and have more use cases, such as the one you've mentioned.

You definitely can do that configuration, and you will need to know how to use the Petalinux to create a bootable image to place on a SD card and boot the PS side of the Zynq.

As an example, you'd create the configuration as below, using the Debug Bridge IP.

XVC_Zynq_image.png

In Block Design, that diagram would translate as something like this (there' some extra IP's such as a counter, just to emulate a logic and allow us to use the ILA).

XVC_Zynq_Block_Design.png

Observe the PS talks via AXI to an AXI Interconnect, which talks to the Debug Bridge (in AXI to BSCAN mode), which talks to the ILA/VIO via BSCAN.

From here, you'd need to generate bitstream and Export Hardware including bitstream.

Now, with the hdf file that has been generated by the export, you can use Petalinux to create a Linux Embedded image for the Zynq (Similar process as explained in the XAPP1251, pg. 11).

 

The following page has more resources on how to use the Petalinux and examples:

https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0016-petalinux-tools-hub.html

 

Please let me know if you have any questions.

Thanks,

Andre Guerrero

Product Applications Engineer

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Visitor derrickg
Visitor
347 Views
Registered: ‎05-04-2016

Re: Using XVC and Debug bridge to chipscope a local Zynq design

Thanks for those diagrams.  That gives me confidence that I have things hooked up right.

I actually haven't ever used peta linux, as we chose to go with Arch several years ago.  Does peta linux have a version of xvcserver that can talk to the debug bridge?  What kernel driver is it using?  I grep'ed the xilinx-2018.2 version of the kernel code and didn't see a 'compatible' string that matched the one in the generated device tree. The closest I have found to a kernel driver was the PCIe one.  I could probably hack it to strip out all of the PCIe stuff and make it a platform driver instead, but if there is already one available then I don't want to go down that rabbit hole.

 

 

0 Kudos
Moderator
Moderator
278 Views
Registered: ‎02-09-2017

Re: Using XVC and Debug bridge to chipscope a local Zynq design

Hi @derrickg,

 

it does not include the XVC application by default. While creating the Petalinux image, you must include the XVC application file in it.

The file is already included in the example design package that you download from the XAPP1251. From the instructions on how to create the Petalinux Image, on step 3 you can see where a template.c file is replaced by the xvcServer.c file, in order to enable such feature.

petalinux_XVC_server.JPG

You can also download the xvcServer.c file from Xilinx Github: https://github.com/Xilinx/XilinxVirtualCable

 

 

Andre Guerrero

Product Applications Engineer

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Visitor derrickg
Visitor
273 Views
Registered: ‎05-04-2016

Re: Using XVC and Debug bridge to chipscope a local Zynq design

Okay. Sounds like the non-PCIe version is still using the UIO driver.  Are there plans to create a custom driver/device node for the non-PCIe version?

0 Kudos
Visitor derrickg
Visitor
250 Views
Registered: ‎05-04-2016

Re: Using XVC and Debug bridge to chipscope a local Zynq design

I was able to get xvcServer working, which is awesome.  Now I am trying to debug an issue that causes the ARM to crash.  It appears that if I select Bypass-mode that I should be able to swap between the soft bscan and the hard JTAG so that I can run JTAG on a processor that doesn't crash.  How to I switch between internal and external JTAG?

0 Kudos