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Adventurer
Adventurer
948 Views
Registered: ‎02-08-2016

Vivado 17.2 fails to implement ILA for debug

Hi,

 

I am using Vivado 17.2 and trying to implement instrumentation I have added to my synthesis.

 

I get the following message:

[Vivado 12-5447 ] synth_ip is not supported in project mode, please use non-project mode.

[Synth 8-439] module 'dbg_hub_CV' not found

......

 

Note this does NOT happen in Vivado 2016.4, and the recommendation of

https://www.xilinx.com/support/answers/60856.html

does not solve this problem.

Is Vivado 2017.2 not fit for purpose for debug mode?

 

Regards SImon

 

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6 Replies
Moderator
Moderator
927 Views
Registered: ‎09-15-2016

Re: Vivado 17.2 fails to implement ILA for debug

Hi @simonh_bwt,

 

If you are trying to generate the synthesis DCP to support the OOC IP flow or to synthesize and implement an IP module in the OOC hierarchical design flow in "project mode", you can try IP run by create_ip_run rather than synth_ip which is a command used in "non-project" mode. I think in the objects you are specifying the IP name, but here the command is giving error. You should get information on these commands in UG835.

 

- Prathik

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Adventurer
Adventurer
922 Views
Registered: ‎02-08-2016

Re: Vivado 17.2 fails to implement ILA for debug

HI Prathik,
I will look at the UG835 documentation. I am not running OOC flow.
Thanks
Simon Hildebrand
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Adventurer
Adventurer
920 Views
Registered: ‎02-08-2016

Re: Vivado 17.2 fails to implement ILA for debug

Hi Prathik,

 

Unfortunately your suggestion does not work because when I run tcl command

create_ip_run [get_ips dbg_hub_CV]  

the system cannot find this IP.

 

Thanks

 

Simon

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Moderator
Moderator
882 Views
Registered: ‎09-15-2016

Re: Vivado 17.2 fails to implement ILA for debug

Hello @simonh_bwt

 

I am not sure of what is being done in your design. If get_ips by default does not return IP names, probably you should check the presence of IP in your design. You can try project mode and check.

 

- Prathik

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Adventurer
Adventurer
801 Views
Registered: ‎02-08-2016

Re: Vivado 17.2 fails to implement ILA for debug

Hi Prathikm

 

Apologies for delay in reply.

 

Thanks for your suggestion.

 

In fact I have been running Vivado in project mode. The IP in question is the Xilinx ILA IP "dbg_hub_CV" which is part of your libraries.

 

This is why I am puzzled. Vivado 2017.2 does not work, Vivado 2016.4 does work. Same project data set, same trial, project mode.

 

Is this a bug in Vivado 2017.2  ?

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Moderator
Moderator
767 Views
Registered: ‎09-15-2016

Re: Vivado 17.2 fails to implement ILA for debug

I am moving this to Design Tools - Others section as this looks ILA specific debug needed.

 

Thanks

Prathik

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