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Visitor pilakkat
Visitor
8,719 Views
Registered: ‎04-27-2009

Vivado 2014.3 instantiating ILA in a package BD subsystem causes all ILA's to fail

Hi

 

I am trying to instatiate an ILA core inside a BD which is packaged as IP and then used in a top level system bd, which also has another ILA. Without the ILA in the subsystem BD everything seems to be OK. But with the ILA in the BD, the design builds fine, but both the ILA's fails (running the immediate trigger doesn't seems to do anything).

 

Appreciate any help.

 

Regards

skp

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Scholar dwisehart
Scholar
8,709 Views
Registered: ‎06-23-2013

Re: Vivado 2014.3 instantiating ILA in a package BD subsystem causes all ILA's to fail

Did you lose your link to the previous time you asked this question: http://forums.xilinx.com/t5/Design-Entry/Vivado-2013-4-Adding-ILA-inside-a-BD-causes-ILA-s-to-fail/m-p/534843

 

What I suggested there is:  Run the timing report.  Are any timing errors reported?  Run the clock internation report.  Are their clock interactions that are not constrained?  It sounds like a cross clock domain problem.

 

ILA cores are successfully used with complex designs and high clock rates.  How full is your FPGA and how much Block RAM do you have available for ILA to use?

 

If you have multiple ILA cores, what do your constraints look like?  Each core needs connection to dbg_core/clk.  Are they sharing the same dbg_core?

 

Daniel

 

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