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Vivado 2017.2 (and 2017.3) resets FPGA if execute open_hw_target command

Posts: 6
Registered: ‎07-26-2017

Vivado 2017.2 (and 2017.3) resets FPGA if execute open_hw_target command


Configuration: Vivado 2017.2, Windows7-64bit, Xilinx USB II JTAG programming cable.
FPGA board with the xcku085-flvb1760 chip. If this FPGA is programmed and I connect to FPGA thru JTAG programming cable, by executing the command in Flow Navigator:   "PROGRAM_AND_DEBUG -> Open_Target -> Auto_Connect "  this FPGA is resetting ( goes to unprogrammed state). This causes problems when debugging eg. PCIe.
Executing connecting command step by step I found the resetting FPGA is happening if execute  open_hw_target command.
Reset occurs only when first connected - the subsequent work of JTAG has no problems.

Versions of Vivado (2016.4, 2017.1) on the same computer configuration and board doesn't reset FPGA if execute the open_hw_target command. I checked two combinations of the source for loading FPGA  (onboard parallel flash and JATG)  and various combinations of power cycle and connection JTAG cable,  in any variants behavior the same. I tested this solution "set_param labtools.auto_update_hardware 0" but no any effect.

In addition, when checking a connection from Vivado 2017.1 I see that it uses hw_server 2017.2 so it seems to me that it's not about the hw_server settings.

The new version of Vivado 2017.3 is the same behavior. Resetting the FPGA after running open_hw_target.

It possible fix this?

Best regards, Roman.

Xilinx Employee
Posts: 247
Registered: ‎08-10-2008

Re: Vivado 2017.2 (and 2017.3) resets FPGA if execute open_hw_target command

Hi, Roman,

Seems a JPROG was issued. Check the Vivado log, is there a boot_hw_device? If there is, move it.
Otherwise, open_hw_target may trigger silently a JPROG; this is useful when you do a remote programming but not in your case.

Don't forget to reply, kudo, and accept as solution.