10-12-2017 02:27 AM
Configuration: Vivado 2017.2, Windows7-64bit, Xilinx USB II JTAG programming cable.
FPGA board with the xcku085-flvb1760 chip. If this FPGA is programmed and I connect to FPGA thru JTAG programming cable, by executing the command in Flow Navigator: "PROGRAM_AND_DEBUG -> Open_Target -> Auto_Connect " this FPGA is resetting ( goes to unprogrammed state). This causes problems when debugging eg. PCIe.
Executing connecting command step by step I found the resetting FPGA is happening if execute open_hw_target command.
Reset occurs only when first connected - the subsequent work of JTAG has no problems.
Versions of Vivado (2016.4, 2017.1) on the same computer configuration and board doesn't reset FPGA if execute the open_hw_target command. I checked two combinations of the source for loading FPGA (onboard parallel flash and JATG) and various combinations of power cycle and connection JTAG cable, in any variants behavior the same. I tested this solution "set_param labtools.auto_update_hardware 0" but no any effect.
In addition, when checking a connection from Vivado 2017.1 I see that it uses hw_server 2017.2 so it seems to me that it's not about the hw_server settings.
The new version of Vivado 2017.3 is the same behavior. Resetting the FPGA after running open_hw_target.
It possible fix this?
Best regards, Roman.
10-23-2017 07:08 PM
01-23-2018 11:35 PM
Lots of our customers are reporting this issue to us. They get a board which has a pre-programmed flash device, they powerup the PCIe system and the FPGA configures from the flash device. They also connect to JTAG, and when they scan the chain with Vivado 2017.2 or higher, the device says "unprogrammed", this is a bad first impression of our products.
I have opened a ticket about this as well: SR#10414726. Are there plans within Xilinx to solve this issue?