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Visitor rednoah
Visitor
1,377 Views
Registered: ‎11-22-2013

Vivado Bug? Block design generated with wrong paraments.

To repeat this bug. Choose project part as xc7v2000t. Create a block design and place an AXI PCIe Bridge with more than one AXI BAR enabled.

vivado_bug_02.PNG

Then assign the address and generate output products. Check the hdl code.

vivado_bug_01.PNG

I found this in vivado 2017.1 to 2017.3.1. But in vivado 2016.4 it's fine.

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4 Replies
1,179 Views
Registered: ‎08-10-2016

Re: Vivado Bug? Block design generated with wrong paraments.

@rednoah,

 

I can see this behavior in 2017.4 as well. Here is my query. It seems only the AXIBAR_0 addresses are updated, and AXIBAR_1 to AXIBAR_5  addresses are not updated at all and retain their default values.

 

Were you able to resolve this somehow? It would be great if you could help.

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Visitor rednoah
Visitor
1,172 Views
Registered: ‎11-22-2013

Re: Vivado Bug? Block design generated with wrong paraments.

Hi @vinay.m.visweswara

Modify the source code manually. You can find the path in the screenshots. Search the wrong addresses and replace them.
Yet every time when you modify the IPI design, everything may be reset.
Use 2016.4 as a temporary solution if possible.

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Visitor neonelm
Visitor
1,108 Views
Registered: ‎02-01-2018

Re: Vivado Bug? Block design generated with wrong paraments.

I have also hit this same issue where only the first C_AXIBAR parameter is correctly being set when generating in IPI.  I have included the bd.tcl file of a simple example on a V7 690 using the PCIe AXI Bridge using 2017.4.  I was also able to confirm that I had this issue with an Ultrascale part that uses the same core.  I didn't check if the Ultrascale Plus which uses the DMA Bridge has this issue or not.

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Visitor neonelm
Visitor
787 Views
Registered: ‎02-01-2018

Re: Vivado Bug? Block design generated with wrong paraments.

Found the solution to setting this in IPI.  In 2016 the PCIe wizard in IPI included the setting of the base and base high addresses, in 2017 this now must be done from the properties tab of the pcie block after it has been added.  See the screenshot.

 

pcie_properties.jpeg

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