11-22-2017 06:16 PM
To repeat this bug. Choose project part as xc7v2000t. Create a block design and place an AXI PCIe Bridge with more than one AXI BAR enabled.
Then assign the address and generate output products. Check the hdl code.
I found this in vivado 2017.1 to 2017.3.1. But in vivado 2016.4 it's fine.
01-22-2018 03:23 AM
01-22-2018 07:04 AM - edited 01-22-2018 07:20 AM
Modify the source code manually. You can find the path in the screenshots. Search the wrong addresses and replace them.
Yet every time when you modify the IPI design, everything may be reset.
Use 2016.4 as a temporary solution if possible.
02-01-2018 09:16 AM
I have also hit this same issue where only the first C_AXIBAR parameter is correctly being set when generating in IPI. I have included the bd.tcl file of a simple example on a V7 690 using the PCIe AXI Bridge using 2017.4. I was also able to confirm that I had this issue with an Ultrascale part that uses the same core. I didn't check if the Ultrascale Plus which uses the DMA Bridge has this issue or not.
05-02-2018 03:39 AM
Found the solution to setting this in IPI. In 2016 the PCIe wizard in IPI included the setting of the base and base high addresses, in 2017 this now must be done from the properties tab of the pcie block after it has been added. See the screenshot.