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Scholar beandigital
Scholar
10,653 Views
Registered: ‎04-27-2010

Vivado Logic Analyser Error

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I am using 2014.3 and get the following errors when I program my board.

 

INFO: [Labtools 27-32] Done pin status: HIGH
program_hw_devices: Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 1716.324 ; gain = 0.000
refresh_hw_device [lindex [get_hw_devices] 0]
ERROR: [Xicom 50-38] xicom: Data structures not initialized for CseXsdb slave Device:0, user chain number/bus:1, slave index:0.
ERROR: [Labtools 27-1829] vcse_server failed during internal command 'CseXsdb_getRegisters'. See previous error messages.

 

 

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Xilinx Employee
Xilinx Employee
18,717 Views
Registered: ‎11-08-2013

Re: Vivado Logic Analyser Error

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Is the timing meeting for this design? Please run report_timing_summary in the implemented design and make sure timings are all met.

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3 Replies
Xilinx Employee
Xilinx Employee
18,718 Views
Registered: ‎11-08-2013

Re: Vivado Logic Analyser Error

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Is the timing meeting for this design? Please run report_timing_summary in the implemented design and make sure timings are all met.

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Xilinx Employee
Xilinx Employee
10,631 Views
Registered: ‎10-24-2013

Re: Vivado Logic Analyser Error

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Hi,
This happens if the design is not timing clean.
Refer to the similar discussion @ http://forums.xilinx.com/t5/Design-Entry/Error-in-Hardware-Manager-when-refreshing-Target/td-p/469812
Thanks,Vijay
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Scholar beandigital
Scholar
10,619 Views
Registered: ‎04-27-2010

Re: Vivado Logic Analyser Error

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Thanks. Just noticed there is a timing error.

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