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Explorer
Explorer
610 Views
Registered: ‎07-28-2008

Vivado block design probling into my own IP?

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I've attempted adding debug in netlist, and going through setup debug wizard. Also setting .xdc processing_order to LATE.

 

Unfortunately, implemented design report not able to find nets.

 

I'm currently starting to add wires to IP IO ports for debugging. Just wonder if I'm using the correct method for probing into my own IP.

 

Regards,

 

 

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Moderator
Moderator
838 Views
Registered: ‎02-09-2017

Re: Vivado block design probling into my own IP?

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Hi @legendbb,

 

Just to clarify, do you go on the netlist, right-click the net and select "Mark Debug" and then open up the Setup Debug Wizard?

 

That process is correct, it should work. 

 

Do you get any errors after the implementation? If yes, please send the errors.

 

Could you also check if the LTX file is being generated, and if it is correct (just open up with a text editor and see if the nets you've marked are there)?

 

Also, did you get to generate the bitstream, open up the HW Manager and program the device? What happens then? Any errors or just no signal shows up?

 

Finally, just as a reminder, the ILA should be used to visualize nets. If you want to see I/O ports, you must use the VIO core, which uses a different instantiation process.

 

Thanks,

Andre Guerrero

Product Applications Engineer

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1 Reply
Highlighted
Moderator
Moderator
839 Views
Registered: ‎02-09-2017

Re: Vivado block design probling into my own IP?

Jump to solution

Hi @legendbb,

 

Just to clarify, do you go on the netlist, right-click the net and select "Mark Debug" and then open up the Setup Debug Wizard?

 

That process is correct, it should work. 

 

Do you get any errors after the implementation? If yes, please send the errors.

 

Could you also check if the LTX file is being generated, and if it is correct (just open up with a text editor and see if the nets you've marked are there)?

 

Also, did you get to generate the bitstream, open up the HW Manager and program the device? What happens then? Any errors or just no signal shows up?

 

Finally, just as a reminder, the ILA should be used to visualize nets. If you want to see I/O ports, you must use the VIO core, which uses a different instantiation process.

 

Thanks,

Andre Guerrero

Product Applications Engineer

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Don’t forget to reply, kudo, and accept as solution.
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