06-03-2019 08:43 AM
Vivado couldn't instantiate debug core getting the following message:
[Labtools 27-3361] The debug hub core was not detected.
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
This message was gnenerated after synthesis/implementation ... in the "Implemented Design" section in Message window.
Nevertheless I checked debug clock ... it comes from PLL IP. (please see screenshot below - bleu line). Can such clock be considered as free-running ?
06-03-2019 09:07 AM
get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]
in the TCL console gets '1'.
06-03-2019 09:35 AM
Well, PLL output isn't actually free-running clock.
I changed debug clock to the external clock and debug core was instantiated.
Yet it does not help me too much, because external clock has almost the same freqeqnce as the signal that I want to debug.
Does exist some way to use PLL sigal as clock source for debug core ?
07-11-2019 10:39 AM
I'm glad you figurred out the issue was with the clocking.
I actually can use the PLL/MMCM as a source of clock for the Debug Core / ILA.
The trick is that you have to make sure that: