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Visitor fk5747
Visitor
343 Views
Registered: ‎03-26-2019

cannot connect another clk to dbg_hub

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Hi,

I am using Artix 7 Evaluation kit, and I wrote some simple VHdl code and now I want to connect the clk_in to the bebug core. The clk_in generates in the code:

i_clock_input : IBUFDS
generic map (
DIFF_TERM => FALSE,
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT")
port map (
O => clk_in,
I => clk_in_p,
IB => clk_in_n
);

I have tried these tow lines in the XDC file:

connect_debug_port dbg_hub/clk [get_nets clk_in]
connect_debug_port u_ila_0/clk [get_nets clk_in]

now there are warning messages :

[Vivado 12-1419] Debug core 'dbg_hub' was not found. 

[Vivado 12-1419] Debug core 'u_ila_0' was not found.

debug.png

and it doent update the clk. Can anyone help me? Thanks in advance.

Regards

 

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1 Solution

Accepted Solutions
Moderator
Moderator
276 Views
Registered: ‎02-09-2017

Re: cannot connect another clk to dbg_hub

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Hi @fk5747 ,

 

How are you implementing the ILA? Are you instantiating it in Verilog/VHDL or are you using the Insertion Flow (Set Up Debug)? or a TCL script? 

If you are using Verilog/VHDL instantiation, the XDC constraints will not work.

If you are doing Set Up Debug or TCL, you should be able to do so with the TCL commands you created (with a post-synthesis design open).

Open the TCL console and issue the command:

get_nets clk_in

Does that returns an object or an empty? If it returns empty, it's because it's not finding such clock in your design. So there might be some sintax issue or something.

Finally, at which point of the design flow you see the errors [Vivado 12-1419] ?

Thanks,

Andre Guerrero

Product Applications Engineer

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Don’t forget to reply, kudo, and accept as solution.
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7 Replies
Scholar dpaul24
Scholar
332 Views
Registered: ‎08-07-2014

Re: cannot connect another clk to dbg_hub

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@fk5747,

A debug block/core can have only 1 clock, which is the design clock. All other signals connected should be non-clock signals.

        ila_core_inst: ila_core
        port map(
            clk        => system_clk_i,
            probe0(0)  => signal1,  
            probe1(0)  => signal2,
            probe2(0)  => signal3,
            probe3(0)  => signal4
        );

The above is how a ILA core should be instiantiated. All signals, namely signal* above, must belong to the system_clk_i clock domain.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
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Visitor fk5747
Visitor
323 Views
Registered: ‎03-26-2019

Re: cannot connect another clk to dbg_hub

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Thank you, but I dont understand your point.

Sorry I am new to Vivado.

Actually I have a problem that the VIvado connects a clk which is not a free running clock to debug core, therefore I follow the answe on below link

https://www.xilinx.com/support/answers/64764.html

and now I am here. Any suggestion?

Thanks

 

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Scholar dpaul24
Scholar
317 Views
Registered: ‎08-07-2014

Re: cannot connect another clk to dbg_hub

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@fk5747,

You want to connect the clk_in to the clock input pin of your debug core, right?

And you are not sure if clk_in  is a free running clock or not?

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
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Visitor fk5747
Visitor
314 Views
Registered: ‎03-26-2019

Re: cannot connect another clk to dbg_hub

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clk_in is a free running clock, I want replace another clk (which is a non-free running clock, and by default connects to the debug core) with clk_in. I hope it make sense?

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Scholar dpaul24
Scholar
311 Views
Registered: ‎08-07-2014

Re: cannot connect another clk to dbg_hub

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@fk5747,

I cannot replace it with another clock which is not a free clock.

as it is mentioned in the AR you have posted, a non-free running clock can have problems. So avoid it!

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
0 Kudos
Moderator
Moderator
277 Views
Registered: ‎02-09-2017

Re: cannot connect another clk to dbg_hub

Jump to solution

Hi @fk5747 ,

 

How are you implementing the ILA? Are you instantiating it in Verilog/VHDL or are you using the Insertion Flow (Set Up Debug)? or a TCL script? 

If you are using Verilog/VHDL instantiation, the XDC constraints will not work.

If you are doing Set Up Debug or TCL, you should be able to do so with the TCL commands you created (with a post-synthesis design open).

Open the TCL console and issue the command:

get_nets clk_in

Does that returns an object or an empty? If it returns empty, it's because it's not finding such clock in your design. So there might be some sintax issue or something.

Finally, at which point of the design flow you see the errors [Vivado 12-1419] ?

Thanks,

Andre Guerrero

Product Applications Engineer

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Visitor fk5747
Visitor
253 Views
Registered: ‎03-26-2019

Re: cannot connect another clk to dbg_hub

Jump to solution

Hi,

Thank you.

I issue the command and I understand that clk_in is not connected to any module. Now it works.

 

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