11-26-2018 10:22 PM
i used VIVADO ILA, get a critical warning as follow:
1) [Labtools 27-3361] the debug hub core was not detected.
and also, when i used ILA core with my design, i get:
2) Timing (38-282) the design fail to meet timing requirement.
i am using zc706 eval. board. i wrote a simple clock divider program by instantiating clocking wizard. i generated a clock of 100mhz from clock wiz by giving it 200mhz system clock.
and i instantiated this clocking IP in my program which will further divide this output clock to some extent so a human eye can detect it on a led.
always @ (posedge clk_100mhz)
then i used VIVADO ILA as:
input clock for ILA, clk_100mhz->clk.
get the errors as mentioned above.
please tell me about:
what should be the clk input frequency for ILA. can i connect same signal to clk and probe as i did?
after connected to Hardware and a Wave form window is opened (when this error "[Labtools 27-3361] the debug hub core was not detected." was not there). i pressed run trigger immediate. now i don't understand what is triggering in ila and how it can be used or where or which signal to be triggered. what sample depth means. please provide me a solution for use of ILA as brief as possible.
my ultimate AIM is to use XADC via DRP port using FPGA Logic and analyze it on VIVADO ILA.
11-26-2018 10:32 PM
Please refer below ILA tutorial to understand the usage/flow.
There are more documentation available on Xilinx site you can check.
Regarding your question, clock of ILA cannot be probed. ILA should have 2x frequency than the probed signal otherwise you will only get constant 1s or 0s.
You should check if the clock is free running or not.
I hope the above pointers will be helpful.
11-27-2018 10:51 PM
Thank you for your reply.
I am facing the following problems:
ILA waveform window is not opening as i connect to hardware device.
Warning : [Labtools 27-3361] the debug core was not detected
Warning : [Labtools 27-3404] Dropping Logic core with cellname : 'LA_1' from probes file , since it can not be found on the programmed device.
I have attached Schematic of my design and Tcl console messages pictures herewith. Please follow the attachments for further information.
Please help me out.
11-30-2018 03:37 PM
Does the output LED in your design works? Do you see it flashing (or can you attach a scope to it to see if there's a signal coming out of it)?
That ILA error is related to not detecting a clock input. Your configuration looks correct (a clock coming out of the Clocking Wizard), so I suspect there might be one of two problems there:
1 - The Clocking Wizard may not be working/not receiving your input clock. How do you assign the clk_p and clk_n to external pins in your device? can you take a look or share your constraints (xdc) file so we can check if the MMCM and clocking constraints are correctly defined?
2 - If the rest of your design works fine, it means we have a problem with the ILA. When you configure the board, what is the JTAG speed you are using? The clocking for the ILA needs to be at least 2.0x faster than the JTAG clock frequency. So try selecting a slower JTAG frequency and reprogramming the board to see if it works.
As a final question, how are you creating the ILA in the design? Are you doing a instantiation in Verilog/VHDL or are you using the Insertion flow after symthesis (Set Up Debug Wizard)?
12-03-2018 01:05 AM
Thank you for your reply
answer 1: yes, the output LED in my design is working correctly.
answer2: I used differential clock input Clocking Wiz. I assign H9 pin to clk_p. I used system clock of 200mhz.
answer3: As follow:
set_property PACKAGE_PIN H9[get_ports clk_p]
set_property IOSTANDARD DIFF_HSTL_II_18 [get_ports clk_p]
set_property PACKAGE_PIN G2[get_ports led]
set_property IOSTANDARD LVCMOS18 [get_ports led]
set_property PACKAGE_PIN AK25[get_ports reset]
set_property IOSTANDARD LVCMOS18 [get_ports reset]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets led_OBUF]
Q4: what is the JTAG speed you are using?
Answer4: I don't know about the JTAG speed. may be you are asking for baud rate, if it is then answer is 115K. if its not then please tell me about this and how jtag speed disturb the ila functionality.
answer5: i instantiated ILA in Verilog.
i also faced the same warnings in different design(using HDL wrapper) as i faced in this design but the ILA waveform window opened and worked correctly.
12-04-2018 01:05 PM
Yes, I mean the JTAG baud-rate.
There's a rule that the JTAG baud-rate has to be at least 2x slower than the ILA clock frequency. Since you have baud-rate = 115K and ILA freq = 200K, it might be part of the issue.
Since your LED works, it's also a good indication that everything is fine with the clock input.
Could you try to lower the JTAG baud-rate (to say, 50K) and try again?
12-11-2018 03:08 AM
Thank you for your reply
I created a block design and then I created HDL wrapper.
Same warnings appears this time also but ILA waveform window opens and working correctly.
A difference I noticed that, in block design dbg_hub and ILA clock was same but in previous case ILA clock was directly from clock wizard output clock and dbg hub taken led_OBUF as clock ( as this is not a free running clock, this may be the reason)
I don't understand what is this and why this is happening.
12-11-2018 04:00 AM