08-09-2017 08:30 AM
i am designing an AXI subsystem with many slaves and masters using the IP integrator. After instantiating the AXI interconnect i want to add my previously generated AXI IPs in the IP integrator design, but the tool does not allow me to add them. The tool only allows me to ADD IPs, but this means that i have to regenerate all the IPs, while it does not allow me to use "ADD MODULE" in order to use my pre-existing IPs.
The only workaround that i have found is to use "make external " function in order to expose the pins of the subsystem to the rest of the project, and then manually route all the AXI cores to the interconnect, but before starting this procedure i want to make sure that there is not other way.
08-09-2017 12:35 PM
The IPI flow calls for your HDL top entity to be wrapped in an IP-XACT IP definition. This allows for the "blue boxes" that you see on the block diagram.
I would recommend opening up your HDL project in Vivado, and then going to Tools -> Create and Package New IP ... and package your HDL as IP-XACT IP block. You then can add the ip repo for your IP to your IPI design-based project, by Tools -> Project Settings, and then select IP from the left side navigation icons. There there is a tab for "Repository Manager". You can point the tool to include the location on disk where you exported your IP-XACT project.
Alternatively, you can do what you described with putting the AXI buses external to the block diagram. This is very tedious, and becomes very difficult to maintain ( especially if you are saying you have a large number of masters and slaves ). Additionally, this can prevent the tools form working as you would expect ( and can lock you out of using other more advanced tools such as SDSoC ). I would highly recommend staying away from this flow.
08-10-2017 03:13 AM
let's consider the following scenario:
- currently I instantiated in the top level of the fpga a couple of ips w/i axi i/f (axi stream, axi Lite and axi4
- I connected the primary IOs of the fpga to the IP primary IOs (e.g. DDR bus and address, Eth PMD, etc.)
What I would like to do is to design an AXI subsystem wrapping these IPs which exposes an AXI master interface and istantiate it in the top level as well as an AXI4 master which implements the application communicating with this subsystem
What is the recommended (smoothest and safest) flow for doing this?
Even in this case I already generated the IPs to be istantiated in the AXI subsystem
thanks so much
08-10-2017 06:00 AM
Hi Tim, thanks for your answer.
I do not understand at what you are referring to when you say "your vhdl". You refer to the top level of the project or the vhdl wrapper of every IP?
What i did is package my top level as an IP, creating a component.xml, and then i added the repository to the project. But this does not allow me to instantiate the ip cores into the IPI.
I ask my question in a clearer way: is it possible to instantiate into the IPI a pre-existing .xci?
Thanks for your time.