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Observer dsavory
Observer
4,326 Views
Registered: ‎06-09-2011

xdl2ncd error "UNEXPECTED RUG CREATION PROBLEM FOR NETWORK"

Hi everyone, I hope this is the correct place for this message.  I am in the process of creating my own router for a school project.  It takes a fully placed, fully UNrouted design in xdl format, parses it, and then routes the design.  The router generates valid XDL.  When I run the command line tool "xdl -xdl2ncd my_routed_file.xdl", I receive an error message that reads "UNEXPECTED RUG CREATION PROBLEM FOR NETWORK".  I haven't the slightest idea what this means.  I am able to successfully generate ncd files in this manner for other xdl designs I have routed.  Only a few routed xdl designs have this problem.  I've google searched for more information, but I can't find anything on the web.

 

Thanks in advance for any answers/enlightenment you can give me.

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2 Replies
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Adventurer
Adventurer
4,302 Views
Registered: ‎12-01-2010

Re: xdl2ncd error "UNEXPECTED RUG CREATION PROBLEM FOR NETWORK"

Hi,

 I also have this problem with the self-designed router for certain net. I've no idea about this problem but simly delete the pips for these nets thave have rug problem.

 

Hope somebody can give any hint!

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Observer joryte
Observer
4,020 Views
Registered: ‎09-21-2011

Re: xdl2ncd error "UNEXPECTED RUG CREATION PROBLEM FOR NETWORK"

I hate to revive old threads, but I hate creating multiple threads on the same subject, especially unanswered threads.

 

I have encountered this error when a net contains multiple branches driving the same wire.  The following (contrived and incomplete) net produces the error (multiple branches driving FAN1):

 

design "design" xc5vlx30FF676-1 v3.2;
inst "CLBLL_X2Y0_SLICEL_X3Y0_inst" "SLICEL", placed CLBLL_X2Y0 SLICE_X3Y0, cfg "D6LUT::#LUT:O6=0 DUSED::0 _BEL_PROP::D6LUT:PK_PACKTHRU:";
net "my_net"
	outpin "CLBLL_X2Y0_SLICEL_X3Y0_inst" D,	
	pip CLBLL_X2Y0 L_D -> SITE_LOGIC_OUTS11,
# Branch 1
	pip INT_X2Y0 LOGIC_OUTS11 -> ER2BEG_S0,
	pip INT_X2Y0 ER2BEG_S0 -> FAN6,
	pip INT_X2Y0 FAN6 -> FAN_BOUNCE6,
	pip INT_X2Y0 FAN_BOUNCE6 -> GFAN1,
	pip INT_X2Y0 GFAN1 -> FAN1,
# Branch 2
	pip INT_X2Y0 LOGIC_OUTS11 -> NR2BEG1,
	pip INT_X2Y0 NR2BEG1 -> FAN4,
	pip INT_X2Y0 FAN4 -> FAN_BOUNCE4,
	pip INT_X2Y0 FAN_BOUNCE4 -> GFAN0,
	pip INT_X2Y0 GFAN0 -> FAN1,
	;

Commenting out one of the pips driving FAN1 alleviates the error and produces an NCD that can be inspected in FPGA Editor.

 

(edited to include inter-tile multi-drivers)

 

A difficult situation to debug arises from bidirectional inter-tile arcs, such as horizontal and vertical LONGs.  The following net also produces the error:

 

net "my_net"
	...
	pip INT_X2Y0 SL2BEG_N2 -> LH18,
        ...
	pip INT_X20Y0 ER2BEG_S0 -> LH0,
	;

 since INT_X2Y0.LH18 and INT_X20Y0.LH0 are bidirectional terminals of the same HLONG arc.  Consequently, my_net is trying to drive both ends.  However, since the drivers are in different tiles, the error is not obvious in the XDL without understanding details of the tile interconnectivity.

 

 

JoRyTe

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