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xilinx vivado static power

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Observer
Posts: 28
Registered: ‎11-02-2017

xilinx vivado static power

hi community, i would really like to know which voltage of this ones will affect the static power in the FPGA?

as you know P(static)=V*I(leakage) so that means if we vary the voltage the static power will be varied!!

voltage.PNG

Moderator
Posts: 8,880
Registered: ‎02-27-2008

Re: xilinx vivado static power

Easy answer,

 

Any voltage supply will affect static power.

 

The supply with the highest static current (vccint) will see the greatest increase in current as voltage increases.

 

CAUTION:  ALWAYS be sure you stay within the recommended supply voltages (Table 2, datasheet).

 

NEVER EXCEED the absolute maximum stated in Table 1.

 

Use the power estimator spreadsheet to see how static current increases with voltages and junction temperature,

 

https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwjp3MH85bnYAhVpsFQKHfXWAPcQFggqMAA&url=https%3A%2F%2Fwww.xilinx.com%2Fproducts%2Ftechnology%2Fpower%2Fxpe.html&usg=AOvVaw2AEy578cyOQZu3L4d-xJIc

Austin Lesea
Principal Engineer
Xilinx San Jose
Observer
Posts: 28
Registered: ‎11-02-2017

Re: xilinx vivado static power

hi @austin, first thanks for replying.

yeah i tried to varied the junction temperture too, and ofcours this it affects the static power. and this my goal is to modelise the static power with voltage and temperture instead of leakage current. i had plot a surface that contains static power, temperature and voltage but i don't know if it would be possible to get the equation of this surface.

 

Moderator
Posts: 8,880
Registered: ‎02-27-2008

Re: xilinx vivado static power

z,

 

I am sure you can fit an equation to your data.  Should not be that hard.  It is pretty much increasing with voltage, or temperature, so it is smooth, non-decreasing everywhere.  A 2 or three order polynomial should easily fit (temperature causes the highest order increase, and voltage will be closer to a linear fit).


Note that you will need to keep data pairs (v, t) together within less than a second (better with 10 ms) or else you will get self heating effects that will skew your results.

 

When we characterize the devices, we use temperature forcing systems to set and regulate the junction temperature +/- 0.5 degree.

Austin Lesea
Principal Engineer
Xilinx San Jose
Observer
Posts: 28
Registered: ‎11-02-2017

Re: xilinx vivado static power

hi @austin, pleaase where can i find the value of the static current in Vivado?

Moderator
Posts: 8,880
Registered: ‎02-27-2008

Re: xilinx vivado static power

You cannot (directly),

 

Detailed Power Analysis is done by running the power analyzer tool (report) in Vivado on a completed design.

 

https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwiyoIjRq7_YAhUH6GMKHcQ7CZgQFggnMAA&url=https%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fsw_manuals%2Fxilinx2012_3%2Fug907-vivado-power-analysis-optimizat...

 

Before the design is complete, you can estimate using the Xilinx Power Estimator spreadsheet.

 

https://www.xilinx.com/products/technology/power/xpe.html

 

Basically, before specifying the bitstream, no power analysis is valid.  It is ONLY after you have your target bitstream that you can determine actual power.

 

Simply the maximum expected static power is in the spreadsheet (also an estimate without a bitstream).

Austin Lesea
Principal Engineer
Xilinx San Jose