cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

A tale of two RoE (Radio Over Ethernet) demos - Simulation

Xilinx Employee
Xilinx Employee
2 0 318

Overview

Enhanced CPRI (eCPRI) is becoming an important technology in enabling next generation 5G wireless applications. The Xilinx Radio over Ethernet Framer (RoE Framer) core is part of a complete eCPRI and Next Generation Fronthaul Interface (NGFI) system solution.

Xilinx provides both simulation projects and a hardware demonstration. This blog entry will help the user to bring up the simulation example, analyze simulated data in the waveform, and demonstrate how to use the demo testbench to apply the user's own configuration.

For the hardware demonstration, there will be a future blog entry called A tale of two RoE demos – Hardware.

The RoE IP provides two simulation example flows, the Block Automation flow and the Open IP Example Flow:

  • The Block Automation flow generates a basic system level simulation example, which includes the 10G/25G Ethernet IP, DMA infrastructure, and a block supporting the IEEE 1588 PTP implementation.This should be used to verify that the system comes out of reset and clocks are running as expected.
    The framer is looped back into the deframer and data flow can be seen with certain configurations. However as this is not guaranteed, data flow simulations should use the example design.
  • The Open IP Example Flow provides a simple example design which only contains the RoE IP and associated testbench files. The demo testbench provides a function to show the user how to control the AXI Lite interface, customize system configuration, and then evaluate RoE IP behavior in simulation.

Block Automation Flow:

1. Create a new Vivado project with the Zynq UltraScale+ MPSoC or RFSoC device family.

2. Create a new Block Design

xud_0-1597667348374.png

3. Add the Radio Over Ethernet Framer in the block design canvas.

xud_1-1597667616892.png

4. Run the first Block Automation. "Cannot add simulation clocks at this time" will be greyed out.

xud_0-1597667830004.png

5. The generated block design will be the hardware demo design if the board type is ZCU102 or ZCU111.

Now Run Block Automation again.

xud_0-1597667930515.png

6. Tick “Connect simple clocks for simulation”

xud_0-1597668022997.png

You can see that clock generator blocks are added to provide stimulus:

xud_1-1597668114137.png

7.In the Sources view, highlight the .bd file, right click, and then create the HDL wrapper after the second block automation.

xud_0-1597668240926.png

8. Find the generated wrapper file under Simulation Sources, and select 'Set as Top'

xud_0-1597668535593.png

9. In Flow Navigator, click Run Simulation -> Run Behavioral Simulation

xud_0-1597668678199.png

10. In the waveform window you can find the roe_framer_0 module in Scope view, and then add the required signals to the waveform:

xud_0-1597668779837.png

11.Force three signals to start the RoE Framer by adding the following commands in the Tcl console:

restart
add_force {/design_1_wrapper/design_1_i/datapath/framer_datapath/roe_framer_0/inst/roe_framer_top_i/fram_disable} -radix hex {0 0ns}
add_force {/design_1_wrapper/gpio_cdc_dipstatus} -radix hex {00000000 0ns}add_force {/design_1_wrapper/design_1_i/ext_reset_in_1} -radix hex {1 0ns}
run 20us

12. Allow the simulation to run for 20us and force another reset:

add_force {/design_1_wrapper/design_1_i/ext_reset_in_1} -radix hex {0 0ns} -cancel_after 40
run all

13. Now you can see the data packets transition behavior in simulation.

xud_0-1597669545023.png

Note: The message interface is the path to the ARM processor, which is not demonstrated in the simulation. This interface can be seen by inserting an ILA in the hardware

Open IP Example Flow

1. Create a new Vivado project with Zynq UltraScale+ MPSoC or RFSoC as the device family.

2. Find the Radio Over Ethernet Framer IP in IP Catalog, double click it and then click OK

xud_0-1597669925076.png

3. Click Skip in 'Generate Output Products'

xud_1-1597669966306.png

4. Right click the roe_framer IP, and then click 'Open IP Example Design':

xud_2-1597670023598.png

5. Only roe_radio_top is added to loop back the data to roe_framer, testbench demo_tb is added as a simulation source.

xud_3-1597670066779.png

6. In Flow Navigator, click Run Simulation -> Run Behavioral Simulation

xud_0-1597670443136.png

7. Now that the simulation is up and running, you can see the signal values in the waveform.

xud_0-1597670565044.png

Configuring ROE using the demo testbench

The Function axi_read_basicExample in the demo testbench shows a basic example. You can simply add it to the initial process to test with it:

xud_1-1597670929122.png

If you want to control ROE configuration, you can use the JTAG2AXI block in the demo testbench.

For example, if you want to transmit control message, you can write register 0xA0006008, and set the message type to #2. Provide the eCPRI Ethertype (AEFE16) value as part of the Ethernet packet header.

xud_0-1597670840452.png

  • 0x6008 is for the eCPRI Data packet Message Type or IEEE 1914.3 RoE data payload subtype.
  • 0x610C is for the packet filter for bit 127-96 of Word 0 message AXI Stream port

A complete register map can be accessed from the  RoE Secure Site

The above register write/read behavior can be observed on the AXI lite interface in the waveform:

xud_0-1597671017011.png

The Tcl console also prints out all of the register values.

xud_0-1597671089218.png

Summary

Now that you know how to generate simulation examples, you can decide which is the most suitable simulation example for you to use as a start point, neither is better than the other.

The upcoming blog entry A tale of two RoE demos – Hardware will provide more details on how to use GitHub wireless_apps to generate a hardware demonstration, get familiar with the xroe_apps API, and run a PTP test. 

References : 

RoE webpage : https://www.xilinx.com/products/intellectual-property/ef-di-roe-framer.html

RoE Product Guide (PG312), which can be downloaded from the RoE Secure Site

10G/25G Ethernet Subsystem IP webpage : https://www.xilinx.com/products/intellectual-property/ef-di-25gemac.html