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AXI Basics 3 - Master AXI4-Lite simulation with the AXI VIP

florentw
Moderator
Moderator
6 14 8,618

Introduction

In the previous AXI Basics articles, we have been through a brief description of the AXI4 specification (AXI Basics 1) and we had an introduction to the AXI Verification IP (AXI VIP) (AXI Basics 2).

In this new entry we will see how we can add an AXI VIP into a Vivado project to simulate an AXI4-Lite interface. We will then look at the signals used for AXI4-Lite transactions in the simulation waveform window.

 

Using the AXI VIP as an AXI4-Lite Master (tutorial)

  1. Download the design files attached to this article

  2. Open Vivado 2019.2

  3. In the Tcl console, cd into the unzipped directory (cd AXI_Basics_3)

  4. In the Tcl console, source the script tcl (source ./create_proj.tcl)

    This will create a Vivado project with a Block Design including an AXI GPIO IP. This AXI GPIO IP has one output connected on its channel 1 simulating a connection to on-board LED that we will try to turn ON/OFF with AXI4-Lite transactions and one input connected on its channel 2 simulating a connection to the on-board switch that we will try to read the state of.


    1.png

     

  5. Add an AXI Verification IP (AXI VIP) to the design.

  6. Double-click on the AXI VIP to open its configuration GUI and change the following parameters:
    1. Interface mode : MASTER
    2. Protocol (MANUAL): AXI4LITE

      3.png

       

  7. Connect the Master AXI4-Lite interface of the AXI VIP (M_AXI) to the slave AXI4-Lite of the AXI GPIO IP (S_AXI) and the aclk and aresetn ports of the AXI VIP to the inputs of the Block Design


    4.png
  8. Open the Address Editor tab (Window > Address Editor) and click on the Auto Assign address icon

    5.png

     

  9. Make sure that the address set is 0x4000_0000

    6.png

    Note: The upper part of the address does not really matter here, because if you check the S_AXI interface of the AXI GPIO, only 9 address bits are connected to the AXI VIP

  10. Validate the block design. You should have no errors or critical warnings.
    Save the block design.

    Now we need to update the test bench file to declare and control the AXI VIP.
    To do so, we will follow the Useful Coding Guidelines and Examples from PG267 (v1.1, October 30, 2019) p46.

  11. Open the test bench file, AXI_GPIO_tb.sv from the Sources window

    7.png

    The test bench file already includes the control of some signals (for example the clock and the reset) and has processes to output the status of the LEDs to the console

     

     

    always @(posedge led_1)
    begin
         $display("led 1 ON");
    end
    always @(negedge led_1)
    begin
         $display("led 1 OFF");
    end

    The first step mentioned in the Useful Coding Guidelines and Examples is to create a module in the SystemVerilog test bench. This is already done in the test bench.

    The second step is to import two required packages: axi_vip_pkg and <component_name>_pkg.

    Note: to find the <component_name> for the VIP instance, use the following Tcl command and find the output corresponding to the AXI VIP instance.
    The attached test bench assumes that the AXI component name is design_1_axi_vip_0_0 (the default for the first AXI VIP added to a BD)

    get_ips *vip*
  12. Add the following lines around line 58

    //Step 2 - Import two required packages: axi_vip_pkg and <component_name>_pkg.
    import axi_vip_pkg::*;
    import AXI_GPIO_Sim_axi_vip_0_0_pkg::*;
     
    Step 3 is to declare an agent of type master VIP

  13. Add the following lines around line 102

    // Step 3 - Declare the agent for the master VIP
    AXI_GPIO_Sim_axi_vip_0_0_mst_t      master_agent;
     
    Steps 4 and 5 consist of creating a new agent and starting it.

  14. Add the following lines around line 107

     
    // Step 4 - Create a new agent
    master_agent = new("master vip agent",UUT.AXI_GPIO_Sim_i.axi_vip_0.inst.IF);
    
    // Step 5 - Start the agent
    master_agent.start_master();


    Everything is now ready to start sending the transactions.

    Sending an AXI4-Lite transaction is really easy. We just have to use the APIs AXI4LITE_WRITE_BURST(addr,prot,data,resp) for a write transaction and AXI4LITE_READ_BURST(addr,prot,data,resp) for a read transaction.

    Note: All of the APIs for the AXI VIP are documented in a zip file which you can download from Xilinx.com here.

    In this tutorial, we will try to toggle the LED_1, which is connected to the AXI GPIO Channel 1, and read the state of SWITCH_1, which is connected to the AXI GPIO Channel 2.

    Looking at the register map for the AXI GPIO IP, per Table 2-4 from (PG144), we have to write at addresses 0x0 and read at address 0x8:

    8.png

    We will start with the write, trying to toggle the state of the LED_1.

     

  15. Add the the following code to write 0x1 to the AXI GPIO register 0x0, which should turn ON the LED

    //Send 0x1 to the AXI GPIO Data register 1
    #500ns
    addr = 0;
    data = 1;
    master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);
     
  16. Add the the following code to write 0x0 to the AXI GPIO register 0x0, which should turn OFF the LED

     
    //Send 0x0 to the AXI GPIO Data register 1
    #200ns
    addr = 0;
    data = 0;
    master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);


    Next we will do a read after each change of position of the switch and display the state of the switch to the console.

  17. Add the following code corresponding the the read transaction:

    // Switch in OFF position
    switch_1 = 0;
    // Read the AXI GPIO Data register 2
    #200ns
    addr = 8;
    master_agent.AXI4LITE_READ_BURST(base_addr + addr,0,data,resp);
    switch_state = data&1'h1;
    if(switch_state == 0)
        $display("switch 1 OFF");
    else
        $display("switch 1 ON");
         
    // Switch in ON position
    switch_1 = 1;
    // Read the AXI GPIO Data register 2
    #200ns
    addr = 8;
    master_agent.AXI4LITE_READ_BURST(base_addr + addr,0,data,resp);
    switch_state = data&1'h1;
    if(switch_state == 0)
        $display("switch 1 OFF");
    else
        $display("switch 1 ON");

     
  18. Launch the simulation and run it for 3us. In the Tcl console, you should see that the LED is toggling and that we are getting the state of the switch

    9.png

    We can now analyze the transactions on the AXI4-Lite interface

  19. In the scope window, select the axi_vip_0 under AXI_GPIO_tb > UUT > AXI_GPIO_Sim_i

    10.png

     

  20. In the object window, right-click on the M_AXI protocol instance and click Add to Wave Window

    11.png
  21. Restart the simulation and re-run it for 3us

    We can see the 4 transactions on the AXI4-Lite interface: 2 write transactions followed by 2 read transactions
    12.png
  22. Expand the M_AXI protocol instance to see the different channels

    We can then see the different steps for a write transaction.
    First, the address is transmitted from master to slave when both the READY and VALID signals are high on the write address channel (AWREADY and AWVALID)


    13.png
    Then the data is transmitted from master to slave when both the READY and VALID signals are high on the write channel (WREADY and WVALID).

    Note: Only one piece of data per address will be transmitted as bursts are not supported on AXI4-Lite interfaces.

    14.png

    Finally the write transaction completes when the slave sends the write response (to tell if the write was successful) on the write response channel. The response is transmitted from slave to master when both the READY and VALID signals are high on the write response channel (BREADY and BVALID)

    15.png
    We can do the same analysis for the Read transaction.
    First the data is transmitted from master to slave when both the READY and VALID signals are high on the read address channel (ARREADY and ARVALID)

    16.png
    Then the data is transmitted from slave to master when both the READY and VALID signals are high on the read channel (RREADY and RVALID).

    17.png

     


    Note: During read transactions, the slave will also send a response to indicate if the read was successful.

    This response will be sent at the same time as the data on the read channel.

Additional Learning

If you want to learn more about AXI, please see the other tutorials in this series:

https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/AXI-Tutorials/td-p/1139107 

14 Comments
alh1027
Observer
Observer

Thanks for the introduction to the use of the VIP.  I see in the simulation and there is a delay between AWVALID being asserted and WVALID being asserted.

Is there an easy way to make AXI4LITE_WRITE_BURST drive those on the same clock cycle?  Would I need to construct the transaction myself using <agent>.wr_driver.create_transaction and set_addr_delay_range and set_data_insertion_delay_range ?

 

Thanks

eskull@0
Contributor
Contributor

I downloaded the zip file (AXI_Basics_3.zip) and ran the tcl script, and added the VIP master. However, the project is missing package AXI_GPIO_Sim_axi_vip_0_0_pkg . Yet the simulation compiled/elaborated without errors or even warnings - how? 

Thank you.

 

florentw
Moderator
Moderator

HI @alh1027 

I do not think this is possible to control from the AXI VIP with the current APIs. I am not sure if adding the delay range will help here

florentw
Moderator
Moderator

Hi eskull@0 

As mentioned in the following topic, the files are not find by vivado syntax checker but they are found during elaboration. The warning on the syntax checker can just be ignored:

https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/AXI-Verification-IP-Simulation/m-p/1144593#M54143 

gianLuilui8
Visitor
Visitor

Hello, and thank you for the great tutorial and information. I have a question about time in between axi4lite writes. In code, is it necessary to specify how long to wait between successive writes (i.e. in your code #200). Or does the VIP take all writes into a queue and sends out writes/reads in a FIFO-like manner? 

florentw
Moderator
Moderator

HI @gianLuilui8 

No it is not required to wait before sending a new transaction. I only added a delay so we can clearly see the 2 transactions on the waveform viewer.

This is only for the visual there is no technical requirement

miamedra2
Newbie
Newbie

Hi,

I'm having issues with the tutorial.  I encounter the following message at step 18 when I launch the simulation.  I'm using Vivado 2019.2.  Can someone please advise?  Thanks!

Best,

Michael

WARNING: Simulation object /AXI_GPIO_tb/master_agent was not traceable in the design for the following reason:
Vivado Simulator does not support tracing of System Verilog Dynamic Type object.
INFO: [Wavedata 42-43] There are no traceable objects to add.
INFO: [USF-XSim-96] XSim completed. Design snapshot 'AXI_GPIO_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 1512.855 ; gain = 0.000

 

capture.png

 

florentw
Moderator
Moderator

Hi @miamedra2 

I am not sure what is the issue here. Few suggestions:

  • Try to reduce the path for the project. I see you are in C:/Users/mmedrano/Do... maybe try directly in C:/
  • Make sure the project is configured as verilog (it should be set this way by the tcl script)

If the suggestions are not helping, I suggest you create a new topic on the forums sharing your project

eskull@0
Contributor
Contributor

Followed the above procedure. Generated output products. Added the code to the test bench as directed.

Problems:

1) The package file axi_vip_pkg file (import statement added at step 12 above) errors not found.

2) ERROR: [VRFC 10-2939] 'xil_axi_resp_t'  errors as an unknown type

Where is the axi_vip_pkg located so that I can add it ? Side note: the only _pkg file produced by the generate output step was the module-specific AXI_GPIO_Sim_axi_vip_0_0_pkg.

What library or pkg do I need to get the xil_axi_resp_t definition? 

I noticed there is a link to the API's in the above description. Downloaded and installed. The axi_vip_pkg was included, along with several other files. After adding that  one file, new errors popped up.

Added the other files that were included in the API download. What I'm left with are 2 files (axi4stream_vip_pkg.sv  and  axi_vip_pkg.sv)  in the Syntax Error Files Sources Heirarchy folder and most of the other added files from the API in the unreferenced file category. 

Attempting to run XSim results in the following errors:

INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/XILINX_VIP_2019_1/Source/axi_vip_pkg.sv" into library xil_defaultlib
ERROR: [VRFC 10-4982] syntax error near 'VIP' [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/XILINX_VIP_2019_1/Source/axi_vip_pkg.sv:68]
ERROR: [VRFC 10-4982] syntax error near 'class' [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/XILINX_VIP_2019_1/Source/axi_vip_pkg.sv:1580]
ERROR: [VRFC 10-2790] SystemVerilog keyword class used in incorrect context [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/XILINX_VIP_2019_1/Source/axi_vip_pkg.sv:1580]
ERROR: [VRFC 10-4982] syntax error near 'class' [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/XILINX_VIP_2019_1/Source/axi_vip_pkg.sv:8777]
ERROR: [VRFC 10-2790] SystemVerilog keyword class used in incorrect context [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/XILINX_VIP_2019_1/Source/axi_vip_pkg.sv:8777]
ERROR: [VRFC 10-4982] syntax error near 'class' [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/XILINX_VIP_2019_1/Source/axi_vip_pkg.sv:9941]
ERROR: [VRFC 10-2790] SystemVerilog keyword class used in incorrect context [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/XILINX_VIP_2019_1/Source/axi_vip_pkg.sv:9941]
ERROR: [VRFC 10-4982] syntax error near 'class' [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/XILINX_VIP_2019_1/Source/axi_vip_pkg.sv:11095]
ERROR: [VRFC 10-2790] SystemVerilog keyword class used in incorrect context [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/XILINX_VIP_2019_1/Source/axi_vip_pkg.sv:11095]
ERROR: [VRFC 10-4982] syntax error near 'class' [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/XILINX_VIP_2019_1/Source/axi_vip_pkg.sv:12003]
ERROR: [VRFC 10-2790] SystemVerilog keyword class used in incorrect context [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/XILINX_VIP_2019_1/Source/axi_vip_pkg.sv:12003]
ERROR: [VRFC 10-4982] syntax error near 'class' [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/XILINX_VIP_2019_1/Source/axi_vip_pkg.sv:12786]
ERROR: [VRFC 10-2790] SystemVerilog keyword class used in incorrect context [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/XILINX_VIP_2019_1/Source/axi_vip_pkg.sv:12786]
ERROR: [VRFC 10-4982] syntax error near 'class' [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/XILINX_VIP_2019_1/Source/axi_vip_pkg.sv:14382]
ERROR: [VRFC 10-2790] SystemVerilog keyword class used in incorrect context [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/XILINX_VIP_2019_1/Source/axi_vip_pkg.sv:14382]
ERROR: [VRFC 10-4982] syntax error near 'class' [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/XILINX_VIP_2019_1/Source/axi_vip_pkg.sv:15899]
ERROR: [VRFC 10-2790] SystemVerilog keyword class used in incorrect context [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/XILINX_VIP_2019_1/Source/axi_vip_pkg.sv:15899]
ERROR: [VRFC 10-4982] syntax error near 'class' [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/XILINX_VIP_2019_1/Source/axi_vip_pkg.sv:16143]
ERROR: [VRFC 10-2790] SystemVerilog keyword class used in incorrect context [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/XILINX_VIP_2019_1/Source/axi_vip_pkg.sv:16143]

INFO: [#UNDEF] Sorry, too many errors..

 

All of above errors occur on lines containing  'topic class member;'  

What is that doing in this package file???

Decided to search in the Vivado install folder for the axi_vip_pkg file, which i found here, \Vivado\2019.2\data\xilinx_vip\hdl. 

Adding that file resulted in the file being classified (in Sources Hierarchy window) as both Unreferenced and Syntax Error file.

Opened the file, discovered another pkg reference, xil_common_vip_macros.svh, tracked it down in Vivado\2019.2\data\xilinx_vip\include.

At this point, all of the pkg files I've added are classified as Unreferenced files, under SystemVerilog, on the Libraries tab in the Sources window. The axi_vip_pkg.sv has thousands of lines marked in red. 

Hmmm. 

Again, I have the Type for these .sv files set to System Verilog. 

 

This seems progressively hopeless, as I often encounter with Xilinx IP. Many hours wasted. Can anyone help? 

 

My environment:  Vivado 2019.2, Win10, project settings - type is Verilog, test bench file set to system verilog.

 

Thank you.

florentw
Moderator
Moderator

HI eskull@0 

Can you share the log without trying any workaround?

Note that  axi_vip_pkg file is shown as not found by the live checker but this is a known limitation. So you should still be able to run the simulation

eskull@0
Contributor
Contributor

Hi,

 

Following is copied from the elaborate.log:

Vivado Simulator 2019.2
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2019.2/Vivado/2019.2/bin/unwrapped/win64.o/xelab.exe -wto 4a85994a999549c5ba02b96474ebfa82 --incr --debug typical --relax --mt 2 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_22 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_6 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot AXI_GPIO_tb_behav xil_defaultlib.AXI_GPIO_tb xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
ERROR: [VRFC 10-2649] an enum variable may only be assigned the same enum typed variable or one of its values [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/AXI_Basics_3/AXI_Basics_3/AXI_Basics_3.srcs/sim_1/imports/sim/AXI_GPIO_tb.sv:127]
ERROR: [VRFC 10-2649] an enum variable may only be assigned the same enum typed variable or one of its values [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/AXI_Basics_3/AXI_Basics_3/AXI_Basics_3.srcs/sim_1/imports/sim/AXI_GPIO_tb.sv:134]
ERROR: [VRFC 10-2649] an enum variable may only be assigned the same enum typed variable or one of its values [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/AXI_Basics_3/AXI_Basics_3/AXI_Basics_3.srcs/sim_1/imports/sim/AXI_GPIO_tb.sv:146]
ERROR: [VRFC 10-2649] an enum variable may only be assigned the same enum typed variable or one of its values [/wrk/2019.2/continuous/2019_11_06_2708876/packages/customer/vivado/data/xilinx_vip/hdl/axi_vip_pkg.sv:11892]
ERROR: [VRFC 10-2649] an enum variable may only be assigned the same enum typed variable or one of its values [/wrk/2019.2/continuous/2019_11_06_2708876/packages/customer/vivado/data/xilinx_vip/hdl/axi_vip_pkg.sv:11730]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

 

The compile.log file is empty.

 

Following is copied from the TCL Console window:

launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/AXI_Basics_3/AXI_Basics_3/AXI_Basics_3.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2019.2/Vivado/2019.2/data/xsim/xsim.ini' copied to run dir:'C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/AXI_Basics_3/AXI_Basics_3/AXI_Basics_3.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'AXI_GPIO_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/AXI_Basics_3/AXI_Basics_3/AXI_Basics_3.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L axi_vip_v1_1_6 -L xilinx_vip -prj AXI_GPIO_tb_vlog.prj"
"xvhdl --incr --relax -prj AXI_GPIO_tb_vhdl.prj"
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:11 . Memory (MB): peak = 2081.547 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '11' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/AXI_Basics_3/AXI_Basics_3/AXI_Basics_3.sim/sim_1/behav/xsim'
"xelab -wto 4a85994a999549c5ba02b96474ebfa82 --incr --debug typical --relax --mt 2 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_22 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_6 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot AXI_GPIO_tb_behav xil_defaultlib.AXI_GPIO_tb xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator 2019.2
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2019.2/Vivado/2019.2/bin/unwrapped/win64.o/xelab.exe -wto 4a85994a999549c5ba02b96474ebfa82 --incr --debug typical --relax --mt 2 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_22 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_6 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot AXI_GPIO_tb_behav xil_defaultlib.AXI_GPIO_tb xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
ERROR: [VRFC 10-2649] an enum variable may only be assigned the same enum typed variable or one of its values [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/AXI_Basics_3/AXI_Basics_3/AXI_Basics_3.srcs/sim_1/imports/sim/AXI_GPIO_tb.sv:127]
ERROR: [VRFC 10-2649] an enum variable may only be assigned the same enum typed variable or one of its values [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/AXI_Basics_3/AXI_Basics_3/AXI_Basics_3.srcs/sim_1/imports/sim/AXI_GPIO_tb.sv:134]
ERROR: [VRFC 10-2649] an enum variable may only be assigned the same enum typed variable or one of its values [C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/AXI_Basics_3/AXI_Basics_3/AXI_Basics_3.srcs/sim_1/imports/sim/AXI_GPIO_tb.sv:146]
ERROR: [VRFC 10-2649] an enum variable may only be assigned the same enum typed variable or one of its values [/wrk/2019.2/continuous/2019_11_06_2708876/packages/customer/vivado/data/xilinx_vip/hdl/axi_vip_pkg.sv:11892]
ERROR: [VRFC 10-2649] an enum variable may only be assigned the same enum typed variable or one of its values [/wrk/2019.2/continuous/2019_11_06_2708876/packages/customer/vivado/data/xilinx_vip/hdl/axi_vip_pkg.sv:11730]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:08 . Memory (MB): peak = 2081.547 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '8' seconds
INFO: [USF-XSim-99] Step results log file:'C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/AXI_Basics_3/AXI_Basics_3/AXI_Basics_3.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Xilinx_Projects/axi_mstr_axi_lite_w_vip/AXI_Basics_3/AXI_Basics_3/AXI_Basics_3.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:20 . Memory (MB): peak = 2081.547 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

 

Please let me know if there is anything else you need.

Thank you.

ES.

eskull@0
Contributor
Contributor

Hi @florentw 

I posted above the log and console output while running in Vivado 2019.2, with the added pkg files. Since you asked for these without "work arounds", I reverted back to the original case (before adding the missing pkg files) and also switched to Vivado 2019.1. The simulation. runs with this setup. So i started over with 2019.2, just simulating without the missing pkg flies (didn't even add the files). This also runs. 

 

Thank you. 

xiaowei6911
Observer
Observer

HI @florentw , I am trying to run this simulation with Vivado 2020.2. i changed the version checking in the tcl files (there are two files) from 2019.2 to 2020.2. will this work? I am having issue with the elaboration stage. it seems is related to the file path. here is a copy of the log file:

Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto eb0b82e4f95a480ab34762edee60bee6 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot AXI_GPIO_tb_behav xil_defaultlib.AXI_GPIO_tb xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
ERROR: [VRFC 10-2991] 'axi_vip_0' is not declared under prefix 'AXI_GPIO_Sim_i' [F:/xilinx_prj/axi_vip/AXI_Basics_3/AXI_Basics_3/AXI_Basics_3.srcs/sim_1/imports/sim/AXI_GPIO_tb.sv:109]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

florentw
Moderator
Moderator

HI @xiaowei6911 

I have not tried in 2020.2 but I guess they should not be too much change

Check the name of the vip using the tcl command mentioned in the tutorial

get_ips *vip*