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AXI DMA MM2S simulation using the AXI VIP core

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This Blog is intended to illustrate the AXI DMA Simulation in Scatter Gather mode using AXI4 VIP cores and the AXI Stream VIP core. The AXI Master VIP configures the DMA in Scatter Gather mode. Scatter Gather Engine reads the Descriptor pointers from the AXI Slave VIP memory model and starts the data transfer. This simulation example shows the data transfer on the MM2S channel.

The example design is created in the 2020.1 version of Vivado® and targets a VC709 evaluation board. The Tcl script for this design and testbench are available in the attachments to this blog entry.


The AXI Direct Memory Access (DMA) IP core provides the direct memory access between the AXI4 Memory mapped and AXI4 Stream Interfaces.

The primary high-speed DMA data movement between the system memory and stream target is through the MM2S (memory mapped to stream) channel and the AXI stream to memory-mapped data movement is through the S2MM (Stream to memory mapped) channel. The MM2S channel and S2MM channels operate independently.

The AXI DMA provides 4 KB address boundary protection and automatic burst mapping, and also provides the ability to queue multiple transfer requests using nearly the full bandwidth capabilities of the AXI4-Stream buses. It has an optional Scatter/Gather Engine.



Figure 1: AXI DMA block diagram


Scatter/Gather mode:

This mode provides offloading of DMA management work from the CPU. The Scatter/Gather Engine fetches and updates buffer descriptors from the system memory through the AXI4 Scatter Gather Read/Write Master interface.



The AXI Verification IP (VIP) core has been developed to support the simulation of customer designed AXI based IP. The AXI VIP core supports three versions of the AXI protocol (AXI3, AXI4, and AXI4-Lite). It can be configured as Master, Slave and pass-through.


AXI Master VIP:  

The AXI Master VIP generates AXI commands and the write payload, and sends it to the AXI system. The AXI Master VIP is used to configure the DMA in this simulation.



Figure 2: AXI Master VIP


AXI Slave VIP:

The AXI Slave VIP responds to the AXI commands and generates the read payload and write responses. The AXI Slave VIP is used as a memory mapped source in this simulation.



Figure 3: AXI Slave VIP

AXI Stream VIP:

AXI Stream VIP has been developed to support the simulation of customer designed AXI Stream based IPs. It generates AXI4-Stream commands and data payload when configured as Master and generates slave AXI4-Stream response when configured as slave. It also checks protocol compliance of AXI4-Stream transactions.


Vivado Block Design:


Address Mapping:


Test bench to simulate the project:

We need to initialize the VIP cores before using them and also need to load the descriptor file in memory which will be used for scatter gather mode.  The complete testbench file is attached to this blog entry.

code snippet to Import the VIP packages into test bench:


Generate the wready and tready of the Slave VIPs.


AXI Master VIP Write register API:


AXI Master VIP Read register API:



Import the attached test bench and mem file to the project and run the simulation.

Once the simulation is done, please check the below status register information in the Tcl console.


Now open the wave form window and check the DMA configuration register on the AXI DMA S_AXI_LITE interface.


 Reading Descriptor pointers from memory over the SG read interface port:


Data Transfer from memory to Stream over the MM2S channel: