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AXI DMA standalone driver test on a VCK190 board

Xilinx Employee
Xilinx Employee
0 0 259


This Versal example design will show how to run AXI DMA standalone application example on a VCK190 evaluation board and is intended to demonstrate use of the AXI DMA standalone driver which is available as part of Vivado and Vitis.

In this blog, we will discuss how to run an AXI DMA bare-metal application to make use of DMA standalone driver in the 2019.2 release. To quick test with design files in the 2020.2 version, refer to this AXI DMA GitHub Example.


Applicable Platforms

  • Vivado and Vitis 2019.2
  • VCK190 ES1
  • Boot Mode: JTAG


Known Issues/Work-arounds

No known issues.

Block Diagram


Design Steps

Step 1:

Create a project targeting a VCK190 ES1 board and Block design in IP integrator.

Step 2:

Add a Versal IP block (Control, Interfaces and Processing System) and run block automation by selecting Memory controller (DDR4), PL clocks and PL resets to 1.


Step 3:

Open NoC Re-customize IP and select the General tab.

Enter the below settings:

  • Number of AXI Slave Interfaces = 7
  • Number of AXI Master Interfaces = 0
  • Number of AXI Clocks = 7


Step 4:

Go to the Connectivity tab and select the connectivity between S0xAXI and MC Port 0 as shown below.


Step 5:

Add the AXI DMA IP and select the configuration settings shown below.


Step 6:

Run validation and check the address editor tab once validation is successful.


Step 7:

Create a top file for BD and run synthesis then implementation and then generate a device image.

Step 8:

Export the hardware design to get the XSA file.

Vitis Steps

Step 1:

Create an application project with a new platform from hardware (XSA) in Vitis.


Step 2:

You can browse an XSA file that is exported from Vivado by clicking the '+" symbol and then clicking next.

Select A72_0 for the CPU then click next, select the Hello World template and finish.


Step 3:

Select the platform.spr file to import the AXI DMA application example project as shown below and then build the project.


Running the Design

Connect to the VCK190 board and run the AXI DMA imported application project.

Example Console Output

Xilinx Versal Platform Loader and Manager
Release 2019.2 Feb 26 2020 - 19:29:05
Silicon: v0, PMC: v1.0, PS: v1.0
[19.752031 ms.] PLM Initialization Time
***********Boot PDI Load: Started***********
Loading PDI from JTAG
Monolithic/Master Device
+++++++Loading Image No: 0x1, Name: psm_fw.elf, Id: 0x1C000000
+++++++Loading Prtn No: 0x1
0.519290 ms. for PrtnNum: 1, Size: 48 Bytes
+++++++Loading Prtn No: 0x2
16.714893 ms. for PrtnNum: 2, Size: 30992 Bytes
32.670668 ms.for Image: 1
+++++++Loading Image No: 0x2, Name: design_1_wr., Id: 0x1C000000
+++++++Loading Prtn No: 0x3
0.004256 ms. for PrtnNum: 3, Size: 32 Bytes
12.203618 ms.for Image: 2
+++++++Loading Image No: 0x3, Name: design_1_wr., Id: 0x1C000000
+++++++Loading Prtn No: 0x4
ERROR: PldHouseClean: Hard Block Scan Clear / MBIST FAILED
891.130171 ms. for PrtnNum: 4, Size: 989024 Bytes
901.011787 ms.for Image: 3
+++++++Loading Image No: 0x4, Name: design_1_wr., Id: 0x1C000000
+++++++Loading Prtn No: 0x5
347.830965 ms. for PrtnNum: 5, Size: 286608 Bytes
357.727771 ms.for Image: 4
+++++++Loading Image No: 0x5, Name: ps_data.cdo, Id: 0x1C000000
+++++++Loading Prtn No: 0x6
0.128134 ms. for PrtnNum: 6, Size: 944 Bytes
12.219009 ms.for Image: 5
+++++++Loading Image No: 0x6, Name:, Id: 0x1C000000
+++++++Loading Prtn No: 0x7
0.139228 ms. for PrtnNum: 7, Size: 336 Bytes
12.305206 ms.for Image: 6
***********Boot PDI Load: Done*************
3735.107181 ms.: ROM Time
[1380.436040 ms.] Total PLM Boot Time

--- Entering main() ---
Successfully ran XAxiDma_SimplePoll Example
--- Exiting main() ---