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Analyze That: Unboxing the RF Analyzer Tool Part 2

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Hello again!

If you read my last blog entry, you will remember that we started to talk about the RF Analyzer tool provided by Xilinx for debugging RF Data Converter designs.

We talked about how this tool allows you to check out the RF Data Converters in a way that is independent of your PCB or the Complete SoC design in the radio application. Then we focused on how the RF Analyzer design is built in the Programmable Logic and how the MicroBlaze is used to manage the communication with the RF-ADC and RF-DAC tiles.

Now we are going to take a look at actually using the RF Analyzer in Hardware.

I’ll talk you through connecting to the board and starting the Application, and then we can road test some of the functionality using the RF Analyzer GUI.

Remember, if you want to download the RF Analyzer GUI and see a tutorial, please request access to the lounge.

Be sure to check out the user guide (UG1309) for a complete guide to using the Analyzer GUI.

Also, the 2019.1 Version of the Analyzer is out now. Please refer to (Xilinx Answer 71746) to understand some of the limitations in the tool for the 2019.1 release. We are always improving it and have added new features, but there are still some things to keep in mind.

ZCU1275 Overview

I had decided to use the Zynq® UltraScale+™ RFSoC ZCU1275 characterization kit here to show how flexible the RF Analyzer is.

Detailed information on the ZCU1275 board and all documentation can be found here.

This image shows the board and the main areas of interest:

zcu1275.jpgIf you remember from the last entry, I said that there was no need to worry about the PCB because the RF Analyzer is independent of your board.

Well, in my particular case this is not strictly true. I do need to know one (or perhaps two) essential things about this board.

You will notice that the connectivity to the RF-ADC and RF-DAC Analog I/O and tile clock inputs is achieved with Bullseye connectors. You can see the pads for these on the left of the device in the picture.

As a result I do need to know the pinouts on these bullseye connectors, but that is all.

Here is how the connector and the Pad are pinned out.

bullseye.JPG

I can cross reference with the Table 1-12/1-13 in the User Guide to understand the ADC and DAC tiles connected to each bullseye. 

There are two options to clock the converters on this board. The bullseye allows me to provide the sample clock to the tiles for the lab equipment, or I can use the RF PLLs on the super clock module to provide the clocks. In this case I need to get the system controller GUI for this board and use it to manage programming of these clocks.

The SCUI for this board can be downloaded on the ZCU1275 landing page.  

The download package provides lots of pre-canned options for programming the RF PLLs on the Analog Super Clock Module.

To make it simple I have decided to provide the sample clocks to the RF-ADC and RF-DAC directly. 

DAC FS is 3932.16Ghz and the ADC will run at 1966.08MHz. This will allow us to transmit the carrier at 3500Mhz (which lines up to the LTE band42 usecase).

We can then receive it with the RF-ADC, and downconvert the signal to recover the baseband data we sent out. 

This is an illustration of the frequency plan. 

frequencyplan.JPG

To acheive this I needed to program the RF PLLA and RF-PLLB to output 3932.16MHz and 1966.08Mhz respectively.

(The board I was using had RF-PLLA connected to the RF DACs and RF-PLLB was connected to the RF-ADC.)

I can connect to the system controller and do this as shown below:

scui.JPG

Ok, so now all of our clocks are set up and the RF-DAC tile0 Channel0 is looped to the RF-ADC Tile0 Channel 0.

We have our bitstream with the Analyzer, so we are good to go!

Launching the RF Analyzer GUI

So let’s get started with the RF Analyzer. If this is your first time using it, you will be prompted to tell the GUI where the installation path to you Vivado or hardware server is.

This is needed because you hw_server is used to manage the connection to the board over JTAG.

vivadopath.png

 

You will also notice that in the background the tool launches the XSDB server. This is to allow communication with the MicroBlaze Application running on the target.

The next step is to boot up the design.

You will be asked to start the hardware server by selecting either the local server, or the remote server if you have a remote machine with the target connected there.sel_target.png

 

Once the hw_server connects you will see the hardware tree that shows what is running on the target.targets.png

 

You can point to your own bitstream as I have done, or you can pick from one of the pre-built bitstreams that come with the RF Analyzer download.

The pre-built bitstream makes use of all tiles. This can be useful if you do not have a Vivado design and you are just bringing up your board in the lab. prog_bitstream.png

Once the bitstream loads and the device shows as "Configured", you will see the MicroBlaze underneath the 29DR device.

You must launch the application on the MicroBlaze. Select the MicroBlaze and press the "Select Target" button. startublaze.JPG

This is the end of the configuration phase, so now we move into working with the ADC and DAC Tiles.

As the application launches you will see the GUI discovering the tile setup and aligning the GUI to the hardware.

In our case we used a single ADC and DAC tile so we can see this configuration mirrored in the GUI.

TileOverview.png

You can select a tile and check its state in the GUI. In this case, both tiles are powered up and they have reached the end state of their start-up state machine. 

So let’s double-check on the converter clocking here. The ADC should have its PLL bypassed and the 1966.08 Sample clock should be coming in.

Similarly, the DAC Tile 0 PLL should be bypassed and the sample clock is coming direct from the board at 3932.16Mhz

adcclock.png

 

dac_clock.png

 

Next let's look at the setup of the RF DAC data path. 

Select Channel 0 in the RF DAC tile and look at how it is set up:dac_datapath.png

You can see that it is set up in IQ to real mode because we plan to send a QAM signal out.

The Mixer is set to 432.16Mhz and interpolation is set to 8x. This means that we will present the upconverted baseband data to the RF-DAC at 432.16Mhz with a sample rate of 491.52Mhz.

Notice that the RF-DAC Nyquist zone is set to zone 2.

This means that the image in the second Nyquist zone at 3500Mhz will be the signal coming out of the DAC. In the loopback, I use a bandpass filter to ensure that it is only this image that is presented to the RF-ADC. 

We use an LVM file to play the stimulus. In the generation tab for the RF-DAC Tile 0 / Channel 0, you must set the signal type to "From File"

In my case I use a 256QAM signal with a bandwidth of about 15Mhz.

See (Xilinx Answer 71687) for an overview of working with data formats.

The GUI will display the baseband spectrum that will be presented to the RF DAC:DAC.JPG

 

To start transmitting this signal, click Generate. 

Next let's look at my RF-ADC data path.

I set the Nyquist zone in this case to be 2. because the signal is in the 4th nyquist zone, it is Even and the Zone 2 setting is appropriate. 

After this you can see that I have chosen the Mixer to provide an NCO frequency of -432.16Mhz, and I decimate by 8. 

This will shift the sampled carrier down to baseband and decimate the unwanted portion of the spectrum. 

 

adc_datapath.png

When I am finished here, I click on the Acquisition button. This brings me to the ADC Tile 0, Channel 0 capture window.

When I click on the acquire button I can see the received signal at baseband. You can also see that the spectrum only extends to 122.88Mhz.

This indicates that the decimation filter is indeed decimating by a factor of 8.

ADC.JPG

This concludes our walk-through of the RF Analyzer.

There are some features I did not cover, for example you also have the ability to experiment with the calibration freezing in the ADC, the threshold detection on the ADC, the QMC, as well as the DAC inverse-sinc.

There is also scope to observe interrupts.

As always I would encourage you to go and experiment with the tool, and try to use it in your debug.