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Basic read/write to AXI BRAM from PS-APU through NoC in Versal

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This Blog entry is intended to illustrate how to access the AXI BRAM from the Versal™ Application processing Unit (APU) through the NoC. 

The example design is created in the 2020.2 version of Vivado® and targets a VCK190 evaluation board. The Tcl script for this design and application code are available in the attachments to this blog entry.

Versal :

The Versal architecture combines different engine types (Scalar Engines, Adaptable Engines, and Intelligent Engines) with a wealth of connectivity and communication capability and a network on chip (NoC) to enable seamless memory-mapped access to the full height and width of the device.

Intelligent Engines are:

  • SIMD VLIW AI Engines for adaptive inference and advanced signal processing compute
  • DSP Engines for fixed point, floating point, and complex MAC operations.

Adaptable Engines are a combination of programmable logic blocks and memory, architected for high-compute density.

Scalar Engines, including Arm® Cortex™-A72 and Cortex-R5 processors, allow for intensive compute tasks.

NoC (Network on Chip):

Network on chip (NoC) is an AXI-interconnecting network used for sharing data between IP endpoints in the programmable logic (PL), the processing system (PS), and other hard blocks.

This device-wide infrastructure is a high-speed, integrated data path with dedicated switching.

Block Diagram


Vivado Steps

Step 1: Create a project targeting the VCK190 board and create a Block design in IP integrator.

Step 2: Add a versal_cips IP (Control, Interfaces and Processing System) and run block automation by selecting Memory controller (DDR4) in the NoC, and set PL clocks and PL resets to 1.


Step 3: Open the NoC Re-customize IP and General tab, and enter the below settings:

Number of AXI Master Interfaces = 1

Number of AXI Clocks = 7


Step 4: go to the Connectivity tab and check the connectivity between S0xAXI and M00_AXI then click OK.


Step 5: Add an AXI BRAM into the block design and click on run connection automation, then select pl_clk0 as the clock source for the slave interface.


Step 6: click run connection automation again to connect to ext_reset_in.


Step 7: Run the validation step and check the address editor tab once the validation is successful.


Step 8: Create the top file for the BD and run synthesis and implementation, then generate the device image.

Step 9: Export the hardware design to get the XSA file. 

Vitis Steps:

Step 1: Create a new application project in Vitis and switch to the "create a new platform from hardware tab".

Click on “+” and browse to the XSA file exported from the Vivado.


Step 2: provide the project name and select the processor.


Step 3: Choose the Hello World Template and click Finish.


Code modifications:

Once the application project has been created, go to main.c and modify the code to write and read the AXI BRAM.

The Xil_Out64 function is used to write the data to the 64-bit address and the Xil_In32 function is used to read the 32-bit data from the address.


Write Data API


Read Data API


Code snapshots


Running the Design

Connect to the VCK190 board in JTAG boot mode and run the application.

Example console output: