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Creating an Acceleration Platform for Vitis Part One: Creating the Hardware Project for the Acceleration Platform in Vivado

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This blog entry is part one of our Simple Guide to Creating an Acceleration Platform for Vitis™. In this entry we will discuss how to enable your platform in the Vivado® Design Suite so that it is acceleration ready in Vitis.

Your platform can be an already established Vivado mature design that you would like to enhance to give you the flexiblity to accelerate software functions. Alternatively the platform can be a simple Vivado design that just has the topology needed for acceleration. The point being that the Vivado design used in the platform does not need to be a one-off design. It should be more organic, and change when your design needs to change.

This is part one of the Simple Guide to Creating an Acceleration Platform for Vitis. You can find the other parts at the links below:

Part Two:  Creating the software project for the Acceleration Platform in PetaLinux 

Part Three: Packaging the Accelerated Platform in Vitis 

Part Four: Testing the Custom Acceleration Platform in Vitis 

Introduction:

When we are accelerating a software component, we are offloading this from the CPU to our accelerated IP in the programmable logic. The Vitis tool will handle adding a datamover between the accelerated IP and the CPU. However, it does need some input from the user. It needs to know what interface to use to connect from the SoC, and the Accelerated IP. It also needs to know which clocks/reset are available to use.

Also, since we will be sending chunks of data between the CPU and accelerated IP, we need an interrupt. And that's basically it... well, there are a few other things we need to tell the Vitis Tool, but we will cover this later.

So, lets get going. Launch Vivado and create your project. I am using a ZCU104 board. However, the steps below are common for all Zynq® UltraScale™ boards, whether it is a development board or a custom board.

Creating the Hardware Design:

Create the Block Design (BD). The name here will be the same name as we will use to name our platform.

stephenm_0-1597226289172.png

Add the Zynq UltraScale Processor Subsystem IP block from the IP catalog. If using a development board, you should avail of the Block Automation feature.

stephenm_1-1597157023766.png

I have changed the default interfaces to include just the LPD:

stephenm_5-1597157692482.png

In our simple platform, we can just create two clocks. These are the clocks that will be used in Vitis.

We can add the Clocking Wizard from the IP catalog:

stephenm_6-1597157734670.png

By default the reset is active high, and our reset source (on the Zynq UltraScale device) is active low. So, we can bear this in mind when in the clocking config.

I have added three output clocks; 100Mhz, 150Mhz, and 300Mhz:

stephenm_8-1597158401526.png

Also, set the reset polarity to active low:

stephenm_4-1597157488686.png

We need to provide a synchronous reset for each clock. We have three clocks, so we need to add three Processor System Reset IP cores from the IP catalog:

stephenm_10-1597158764315.png

Next, we need to add the interrupts. Here, we can add an AXI Interrupt Controller from the IP catalog. Users can avail of the Run Connection Automation feature that is available in the IP Integrator to handle the AXI connections.

Use the 100Mhz clock:

stephenm_11-1597158830387.png

In the AXI Interrupt Controller, set the Interrupt Output Connection to Single and connect this to the pl_ps_irq on the Zynq UltraScale IP:

stephenm_12-1597158905002.png

This is all we need for a basic hardware platform.

Now we just need to set the metadata to tell Vitis about our hardware via the Platform (PFM) properties.

Adding the PFM properties:

The PFM properties are needed to pass the metadata to Vitis.

Vitis extracts this data to determine what interfaces, clocks, and interrupts can be used to add the accelerated portion to the existing platform.

Platform Name:

First, we need to give our Platform a name:

set_property PFM_NAME {<vendor>:<board>:<name>:<revision>} [get_files [current_bd_design].bd]
set_property PFM_NAME {xilinx:zcu104:zcu104_base:1.0} [get_files [current_bd_design].bd]

Once this is done, you will see a new Platform tab. Here all of the clocks, interfaces, and interrupts in the entire design will be visible.  We need to filter what resources can be used in Vitis.

Enable Clocks:

Right click on the clock, and select enable:

stephenm_0-1597159599898.png

Repeat for clk_out3

Clock Properties:

Select the Options tab:

stephenm_1-1597159801228.png

Note: The clock id must start at 0 and increment so change this here. We must also specify a default.

The default here is the default clock used in Vitis:

stephenm_2-1597159949819.png

Set the index for clk_out3:

stephenm_0-1597160065760.png

Enable Interfaces:

This can be any interfaces that are available in our block design, for example the interfaces on the Zynq UltraScale device or the interfaces on the AXI interconnect.

In this case, I will just add the interfaces on the Zynq UltraScale device. 

 

stephenm_2-1597160340667.png

Enable Interrupts:
set_property PFM.IRQ {intr {id 0 range 31}} [get_bd_cells /axi_intc_0]

Project Properties:

The Vitis IDE is a unified tool that supports a lot of different flows such as Data Center, Acceleration, or Embedded. We need to pass this intent to the Vitis tool.

If we intend to create an Embedded design, we need to specify this. In our case we intend to use Vitis to accelerate. This needs to be specified because Vitis needs to tell the downstream tools how to handle the platform. 

These properties can be seen here:

set_property platform.default_output_type "sd_card" [current_project]
set_property platform.design_intent.embedded "true" [current_project]
set_property platform.design_intent.server_managed "false" [current_project]
set_property platform.design_intent.external_host "false" [current_project]
set_property platform.design_intent.datacenter "false" [current_project]
 

Creating the XSA:

Complete the following tasks to create the XSA:

  • Generate the Block Design
  • Create the HDL wrapper
  • Generate the Bitstream
  • Select File -> Export -> Export Hardware
    • Select Expandable -> Pre Synthesis, and include Bitstream

User can enter the details here:

stephenm_0-1597228398976.png

 
And that's it.
 
For the next steps, see part two of this series: Creating the software project for the Acceleration Platform in PetaLinux