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Debugging PCIe Link Training Issues Part One

Xilinx Employee
Xilinx Employee
1 0 658

When working on a design using a PCI Express IP, it is wonderful when the link is established with the link partner on the very first attempt. However, sometimes the link does not come up straight away.

A successful PCI express link is the result of the products from two different vendors working together. If the link fails, the issue could be on either side.

Users tend to put the blame on the FPGA, but based on our experience, the issue is just as likely to be related to the link partners (for example, the host machine, chipset, board, switch etc.).

We will discuss these scenarios in our future blog entries.

In this first blog entry, I would like to cover how you can do analysis of the debug signals related to link training when you run into link up issues.

To do this, you can capture the signals in Vivado ILA and compare the toggling of the signals with the waveform generated by simulating the example design. You will need to manually pull the corresponding signals into your simulation waveform.

The answer record below describes how to use Vivado ILA for debug by capturing link training debug signals in the UltraScale FPGA Gen3 Integrated Block for PCI Express core.

The document provided does not go into detail on the background of link training issues, but following the steps included should provide significant insight into the probable cause of an issue.

https://www.xilinx.com/support/answers/71355.html