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Debugging Versal ACAP Integrated Block for PCI Express link issues using in-built "PCIe Link Debug" feature

Xilinx Employee
Xilinx Employee
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The Versal™ ACAP Integrated Block for PCI Express® customization provides an option to enable PCIe® Link Debug.

Enabling this option will insert a debug core inside the IP core that will be recognized by the Vivado Hardware Manager and provide PCIe specific debug information and view.

The debug view provides information relating to the current link speed, current link width, and LTSSM state transitions, which can facilitate debug of PCIe link related issues.

This is a new feature introduced for Versal devices. Similar features are available for UltraScale and UltraScale+ devices which require users to go through additional steps. These features are documented in an earlier blog entry here.

For Versal devices, Vivado has an in-built debug cockpit where the LTSSM diagram and other debug related information is displayed within the Vivado GUI framework.

This blog is an addendum to the "PCIe Link Debug Enablement" Appendix provided in (PG343). The blog provides detailed steps with screenshot for each, for better clarity and conceptual usage.


Design Generation:


Select the VCK190 Board. The design illustrated in this blog is for Vivado 2020.2.

Make sure that the board device selected in Vivado matches with the device on the board. An earlier version of the VCK190 board contains an ES1 device. 


Select 'Versal ACAP Integrated Block for PCI Express (1.0)" from the IP Catalog. To use the in-built debug feature, "PCIe-Link Debug" and "Enable Debug AXI4 Stream Interfaces" must be selected as shown below.

Link parameters can be set to Gen3x8 as shown below. If you are running into link training issue, try with a Gen1x1 configuration first.


Once the IP is generated, you will see the following in the 'Sources' window. 


To use CIPS MIO 38 as a reset source, set insert_cips to true before opening the example design as mentioned in the screen capture from (PG343) below.

This will forward the reset from the MIO pin to the  Versal ACAP Integrated Block for PCIe Express IP (PL PCIe).

Make sure that you see the mio_pl_38 pin in the CIPS connected to pcie_phy and PL PCIe. This is shown highlighted in orange in the schematics diagram shown below.




Right Click and then click on 'Open IP Example Design' to open the example design that comes with the IPRight Click and then click on 'Open IP Example Design' to open the example design that comes with the IP

The screen capture above shows an option to generate an example design that comes with the IP.
Click on 'Open IP Example Design'. This will open a new Vivado project with the file hierarchy in the sources window of the new project, as shown below.







Make sure that the REFCLK and GT LOC constraints are as shown below. These constraints are required for a VCK190 board. These constraints are generated automatically when you select a VCK190 board.


If you are using a VCK190 board with an ES1 device, you need to apply a work-around.

Set the corresponding parameters for PMC MIO 37 as shown below:


After the above change, you will need to update the IP. 


After implementing the example design, verify that the I/O ports and Clock are mapped to the pin locations and the QUADs shown below.

The below shown pin locations are required for a VCK190 board. 


PCIe Debugger


After generating the device image, download the generated PDI and LTX files. Straight after downloading the image, you should see the LTSSM diagram as shown below.

This is a new debug feature added for Versal devices. This feature is not currently supported for earlier device families such as UltraScale and UltraScale+. The similar debug feature available for UltraScale and UltraScale+ devices requires that you run separate Tcl files to generate the LTSSM diagram. 



• Green color – transitioned state during the capture window
• Orange color – last state
• Red arrow – last transition state
• Numbers beside the arrow – indicates the number of times the transition happened between the two states

There are additional debug features that you can extract from the debug cockpit. If you check PCIe Debug Core Properties, it gives the lane status and which quad number has PCIe Lane-0.


Similarly, the GT status can be read from the corresponding GT properties window. 



In the Tcl window, you can execute the report_hw_pcie command as shown below.

This will output the general PCIe status and also it provides a list of ltssm states and whether these states were visited or not during the link training process.


There are a few options that you can apply with the report_hw_pcie command. You can find the details within help as shown below:


The other available commands for PCIe are as follows:

  • get_hw_pcies
  • reset_hw_pcie
  • refresh_hw_pcie

If you select LTSSM state in the PCIe Debugger window, the corresponding ltssm bit decoding is displayed in the PCIe State Properties window.


The full list of ltssm bit decoding can be found in the product guide or you can see the list when you run the report_hw_pcie command as shown below.


In-System IBERT


You can easily generate an eye-diagram in the debug cockpit. You will need to first Create Links. All of the steps are shown below and are self-explanatory.













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