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Differences between Designing with UltraScale+ CMAC and Versal MRMAC

ejanney
Xilinx Employee
Xilinx Employee
5 0 495

The Multirate Ethernet MAC (MRMAC) provides high-performance, low latency Ethernet ports supporting a wide range of customization and statistics gathering.  The MRMAC includes a variety of new features and design flows that enable seamless rate change, statistics management and integration with the GT blocks. 

This blog is intended to help customers with 100G Ethernet (CMAC) hard block or soft 10G/25G/40G or 50G Ethernet IP core experience to design efficiently with Versal™ MRMAC. The blog will cover key differences between the UltraScale+ and Versal IP including:

  • Multi-Rate Considerations
  • AXI Stream Interface for Packet Data
  • New MRMAC Flex Port Feature
  • Statistics and Management 
  • 1588 PTP Support
  • Design Flow Considerations
  • Getting Started with the Versal MRMAC Example Design

Multi-Rate Considerations

 

In UltraScale+ the hardened CMAC block supported 100G Ethernet.  MRMAC provides wider customization for line rate, clocking, and user interface.

Supported configurations are:

  • 1 x 100GE
  • 2 x 50GE
  • 1 x 40GE
  • 4 x 25GE
  • 4 x 10GE

The MRMAC architecture is composed of four independent Ethernet ports, each capable of 10/25GE data rate. The port resources can be dynamically combined to produce higher IEEE Ethernet rates, up to an overall bandwidth of 100GE. The ports can be statically configured through the IP wizard or dynamically configured during run-time through the AXI4-Lite interface.

Port 0 can be configured to operate at 10GE, 25GE, 40GE, 50GE, or 100GE data rates. However, when operating at 50GE data rate, port 0 consumes the data path resources of port 1, making it unavailable for independent operation. When port 0 is configured for 40GE or 100GE data rate operation, all internal data path resources are consumed. Consequently, ports 1, 2, and 3 are unavailable for independent operation.

AXI Stream Interface for Packet Data

 

MRMAC now has an integrated AXI4-Stream Interface for MAC+PCS operation as opposed to CMAC, which offered an integrated 512-bit LBUS interface with an optional soft AXI Stream Interface.

Various AXI4-Stream bus widths and clocking options are available and depending on configuration, vary from those available in UltraScale or UltraScale+ device CMAC or soft core solutions.

The AXI4-Stream interface is dynamically re-configurable during run-time to support the selected mode of Ethernet operation. The MRMAC AXI4-Stream interface can be configured as four independent interfaces or combined together as a wider bus to support the higher data rates. The number of 64-bit data word lanes can be configured to tailor the interface towards low latency performance or low frequency clock rates (Independent clock mode).

(PG314) Table 4: MRMAC AXI4-Stream Modes provides the various AXI4-Stream clock rates and data widths supported for the data rate configuration for each interface.  In the Independent clock mode the AXI4-Stream interface can run at a minimum of half of the core clock rate.

Currently the MRMAC IP core exposes all ports of the AXI4-Stream interface to the user to allow for dynamic reconfiguration over AXI4-Lite.  (PG314) AXI4-Stream Interface Table 14: 10G Non-Segmented Signaling for 32 Bits through to (PG314) Table 25: 100G Segmented Signaling for 384 Bits cover which ports of the AXI4-Stream interface are used for each configuration. 

New MRMAC Flex Port Feature

 

MRMAC provides a new Flex Port option for access to the PCS level and FEC only mode. See (PG314): Flex Interface Modes for more information.  

Statistics and Management

 

In UltraScale+ CMAC, most runtime configuration, status, and statistics were provide as ports on the hard block with optional soft AXI4-Lite interface.  The CMAC did have a DRP register interface to access configurations that were typically fixed in the IP via the core configuration GUI.  For Versal MRMAC, integrated hard block registers are used for configuration, status and statistics: 

  • Users access MRMAC integrated registers over the AXI4-Lite interface. The MRMAC hard block has an integrated APB3 register interface and the MRMAC IP core provides access to the APB3 registers over the AXI4-Lite interface.  
  • Basic status information such as stat_rx_block_lock, stat_rx_aligned, stat_rx_status is provided via both ports and registers
  • Some common runtime configuration and resets are provided as both ports or registers
  • Mode and rate changes are done over AXI4-Lite
  • Instead of the provided statistic counter increment vectors, statistics registers are now integrated as part of the hard block accessed over AXI4-Lite
  • Additional configuration and status information is provided only via the register interface 
  • Register definitions are available in a spreadsheet that can be downloaded from the MRMAC product documentation page
  • Configuration and status ports are available in (PG314) Table 35: MRMAC Control Port Descriptions and Table 36: MRMAC Status Port Descriptions

1588 PTP Support

 

The MRMAC also supports a new high-precision timestamping feature to enable sub nanosecond accuracy on IEEE Std 1588 timestamps.

Design Flow Considerations

 

There are two main design tools when targeting Versal ACAPs:

  • Vivado Tools Design Flow to accelerate high-level FPGA design and verification
  • Vitis™ Environment Design Flow to build accelerated applications

In UltraScale+ the GT is included in the IP by default with an option for it to be moved outside the core.  The GT is not included as part of the MRMAC core or other Versal ACAP Ethernet IP.  IP integrator block automation is used to connect between the MRMAC and GT.  To connect the MRMAC to the GT via block automation:

1) From Vivado Flow Navigator, Create or Open an IP Integrator block design:

ejanney_0-1614138164014.png

2) Click the + button to select and add the MRMAC IP to the block design.

ejanney_0-1614138530052.png

3) Double click on the the MRMAC core block to open the configuration GUI and to make changes to configuration mode, MRMAC location and GT reference clock rate.  

ejanney_1-1614138870425.png

 

4) Select Run Block Automation to connect to the GT:

ejanney_2-1614139029603.png

 

ejanney_3-1614139114570.png

5) Block Automation Connects the MRMAC to the GT Quad Base and adds GT clock buffers:

ejanney_4-1614139355580.png

 

Additional Design Flow resources:

  • (PG331) Versal ACAP Transceivers Wizard LogiCORE IP Product Guide
  • (PG314) Appendix A for Clocking Use Cases.
  • (Coming soon) Differences when Designing with UltraScale+ GTY and Versal GTY - for more information on the GT IP Integrator flow, IP to GT integration, pin planning, rate change without the need for DRP, APB connection, and IBERT.
  • For assistance using IP Integrator, visit the Vivado – Using IP Integrator Design Hub.  
  • (Coming soon) Quad sharing example .
  • Note: all Versal ACAP designs require the CIPS IP as it contains the PMC used to boot the device. For more information, see the Control Interface and Processing System IP Product Guide (PG352)

Getting Started with the Versal MRMAC Example Design

 

To get started with the Versal MRMAC, step through the example design documented in Chapter 6 of the Versal Devices Integrated 100G Multirate Ethernet MAC (MRMAC) LogiCORE IP Product Guide (PG314)

This example design demonstrates switching speeds between 1x100GE, 1x50GE, 1x40GE, 4x25GE, and 4x10GE.  The design shows a mixed RTL and IP Integrator design flow.  The recommended IP Integrator usage for the MRMAC to GT Quad Base IP connections, BUG_GT connections, and CIPS are included in Block Designs while the rest of the design is Verilog RTL.

The example should additionally be reviewed to understand the required clocking and reset connections between the MRMAC and the GTs.

In simulation, the Verilog testbench executes AXI4-Lite register writes to configure and change rates, start the packet generator and read RX statistics.  For Hardware testing, C-code is provided to build a software application in Vitus for the AXI4-Lite register read and writes. Chapter 6 of (PG314) provides step by step instructions for running simulation and targeting the hardware example design to a VCK190 or VMK180 board. 

The example design can be generated by right clicking on the MRMAC IP in IP Integrator: 

ejanney_0-1614139869106.png

 

 

References

 

  • For more information on the MRMAC, see the Versal Devices Integrated 100G Multirate Ethernet MAC (MRMAC) LogiCORE IP Product Guide (PG314)
  • For more information on the Versal ACAP GTY and GTYP Transceivers, see the Versal ACAP GTY and GTYP Transceivers Architecture Manual (AM002)
  • For more information on the Versal ACAP Transceivers Wizard, see the Versal ACAP Transceivers Wizard LogiCORE IP Product Guide (PG331)
  • For more information on the differences designing with UltraScale+ GTY and Versal GTY, including information on the GT IPI flow, IP to GT integration, pin planning, rate change without the need for DRP, APB connection, and IBERT, see the Differences when Designing with UltraScale+ GTY and Versal GTY blog entry (coming soon).
  • For more information on IBERT, see the Vivado Design Suite User Guide Programming and Debugging (UG908)