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How to debug the Versal PLM in Vitis

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In this blog we will discuss how to debug the Platform Loader Manager (PLM) in Vitis™.

The PLM architecture is discussed in UG1304 . This blog will not discuss the complexities of the PLM. It will try to give some ideas on how we can debug the PLM not only for debugging purposes, but for exploratory purposes also.

This is the second blog in the Versal "from the ground up" debug Series. Users can see previous blogs in this series here:

Hardware Design:

The Hardware Design used here is shown below:


Create the PLM executable:

There is a PLM included in the PDI. See the blog here for more info on the Versal™ boot files.

However, this PLM would not have the debug symbols added that would be needed to debug in Vitis. The PLM uses the PLM Interface to handle the tasks. This 

is delivered in its own library. So, we will make a local copy of this library and remove the optimization and the Link Time Optimization here too via the makefile.

Making a local copy of the PLM Interface Library

We will be making a local copy of this library. I have copied this from the Vitis Install to a local directory:


Here we can update the MakeFile in the src directory to remove the optimizations. The MakeFile COMPILER, ARCHIVER, EXTRA_COMPILER_OPTIONS, ect are 

all populated from the toplevel MakeFile. To update the compiler options, we can change the EXTRA_COMPILER_OTPIONS as shown below:



EXTRA_COMPILER_FLAGS=-g3 -O0 -ffunction-sections -fdata-sections -Wall -Wextra



Users can also enable the debug print statements. To do this, open the xplmi_config.h, and uncomment the PLM_DEBUG_INFO #define


Add this custom Library to the Vitis Repository (Xilinx -> Repository):



In this blog we shall be creating the PLM in Vitis using the templates as shown below:


Select the Versal PLM template:


If the users sets the build type to Debug and build then the -g -O0 compiler flags will be added.

This will both add the symbol info, and remove optimization so that users can debug the app in Vitis.


We now need to replace the PLM in the PDI with our PLM which we created in Vitis.

This is covered in (UG1283)

Users can use the below BIF template:



 { type = bootimage, file = base.pdi }
 { type = bootloader, file = plm_debug.elf }



Then use the bootgen command below:

bootgen -arch versal -image bootgen.bif -w -o BOOT.BIN

This PDI can then be part of a bigger boot image or just be used as-is. 

Setting up the Vitis Debug:

Here, we will be attaching to a running target in the Debug Config:



Place the updated boot image on the SD card and boot the Versal™ device

Then in the XSCT, add the symbol file:

target -set -filter { name =~ "MicroBlaze PPU*"}
memmap -file plm_debug.elf
bpadd &main
bpadd &XPlm_Init


Here we can see that the Breakpoint was added at 0xf0232050. We can double check this in mb-objdump:


Then preform a reset rst -proc, and the breakpoint at main should be hit first:


Then, if I resume I should hit the breakpoint in the PLM Interface:


Where Next? 

Debugging PetaLinux Versal Boot Images in Vitis 

In this blog entry we will discuss how we can debug the Versal™ boot images such as the ATF, U-boot (pre and post relocation) in Vitis™