There are a host of IP cores available on the Versal™ Control, Interfaces and Processing System (CIPS) that users can access from the APU or RPU on the CIPS.
However, in this blog we will instead discuss how we can leverage these IP cores from a Soft Processor in the Programmable Logic. In this blog the Soft Processor will be the MicroBlaze. I will show how you how to execute from the PS DDR and how to leverage the UART on the CIPS.
The Hardware Design:
Launch Vivado, target the VCK190 board and create a Block Design (BD):
You can make use of the Run Block Automation utility:
In the resulting page on the GUI, select the DDR and then enable the PL Clock and Reset:
This will add the CIPS and the NoC (The NoC provides a path from the DDR to the CIPS):
Note: you can remove the sys_clk0 and the CH0_DDR4_0 pin/port and all nets between the CIPS and the NoC here as we will be using the board connections here.
Next, we need to configure the CIPS. Double click on the CIPS BD cell in the IP Integrator canvas to open the config GUI.
As we are targeting the VCK190 board, you can pick the preset config settings.
If you are on a custom board, you can manually enable the MIO settings based on your needs.
Select PC-PMC -> NoC and configure as shown below:
Select PC-PMC -> PS-PL Interfaces and configure as shown below:
Next, Double click on the NoC from the IP Integrator canvas, and configure as shown below:
Then connect as shown here:
Then run the Run Connection Automation utility:
Note: this is a good starting point for most users to evaluate Versal in Vitis.
However in this case, we will be adding the MicroBlaze.
So let's do that.
Add the MicroBlaze from the IP catalog:
Again, we can make use of the Run Block Automation utility:
I have chosen to omit the LMB BRAM here, as I will show how we can use the DDR via the NoC as executable memory to save BRAM resources:
This will result in a system similar to the following.
The MicroBlaze will be connected to the DDR via the NoC. To do this, we need to add another slave port and clock on the NoC.
Double click on the NoC BD cell in the IP Integrator canvas and configure as shown below:
Add a new AXI SmartConnect (call it axi_smc_memory), and use this to connect the MicroBlaze to the DDR (via the axi_noc_0):
We need to enable the debug port on the CIPS:
We also need to enable the bscan port on the MDM:
Then connect as shown:
We shall be clocking and resetting the clocking wizard from the CIPS.
So we need to configure the input clock and reset as shown below:
Then connect as shown:
Because we are executing from DDR, we need to hold the MicroBlaze in Reset until the DDR is calibrated. To ensure this, we can use the discrete ports on the MicroBlaze, and set the MicroBlaze in a reset mode until it is awoken. We can control the wakeup by using a GPIO on the CIPS.
Firstly, double click on the MicroBlaze BD cell in the IP Integrator canvas and enable the Discrete ports as shown below:
Use a constant IP set to 01 to drive the reset_mode on the MicroBlaze:
Next, we can add a GPIO on the CIPS to control the wake-up:
Connect the Proc reset pin to the PL reset pin:
Next, we can add another AXI SmartConnect (called axi_smc_periph), and connect from the MicroBlaze data port to the CIPS LPD.
Configure this AXI SmartConnect as shown below:
Then connect the MicroBlaze data port to the CIPS LPD:
Note: All of the clk pins are connected to the clock wiz clk_out1 and the reset to the respective pin on the proc reset IP.
Validate the Design:
The assign the slaves in the Address Editor:
Make sure that the address map covers all of the IP cores:
We are now ready to implement the design and export to Vitis™:
Generate the Block Design
Create the HDL wrapper
Generate the Device Image
Modifying the PDI file:
The MicroBlaze is held in reset, until woken by the wakeup pin. The wakeup pin is controlled by the GPIO. To toggle the GPIO, we can create a custom CDO file.
Note: See the blog here for more information on the Versal boot files.
First create a .txt file with the following contents: