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PS IIC and AXI IIC debug techniques

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In the "IIC Protocol and Programming Sequence" blog entry, we provided a detailed explanation for beginners of the Inter-Integrated Circuit (IIC) protocol basics and programming sequences.

In this blog entry, we will discuss debug techniques for AXI IIC and PS IIC.

PS IIC programming sequence debug: 

 

The controller is set as Master transmitter.

  1. Enable the PS IIC in the Zynq-7000/Zynq UltraScale+ device. Make sure that SCL is configured for either 100 kHz or 400 kHz frequency.
  2. Set the control register for the Master transmitter controller. 
  3. Check if the interrupts are clear and that the clock dividers are configured for the actual SCL.
  4. To test communication with a slave device, write to the PS I2C address register (I2C_Address) with the slave address followed by data into the I2C_data_reg
  5. The HOLD bit should be handled based on the data size. When the data size is less than the FIFO depth, clear the HOLD bit to terminate the transaction and generate the STOP bit. 
  6. Slave device acknowledge (ACK) can be monitored by ISR after enabling NACK to interrupt in Interrupt enable register (IER)
  7. Verify that the COMP flag bit in the ISR is set. This tells you that that data transfer is successful
  8. If the master transfer is not successful, the user can debug using the steps below:
    • Make sure that the configurations are correct in the control register
    • Check the NACK bit in the ISR to confirm the slave's response
    • Take care of the HOLD bit as outlined above. Otherwise it will cause SCL to pull down until timeout
    • Monitor the TXDV bit in the status register to check if there is any pending data to be transferred
    • The Bus busy or BA bit in the status register will help you to understand the bus condition during the data transfer.

 

The controller is set as Master receiver

  1. Same as step 1 for the Master transmitter, enable the PS IIC in the Zynq-7000/Zynq UltraScale+ device. Make sure that SCL is configured for either 100 kHz or 400 kHz frequency.
  2. Using the software application, set the control register for the Master receiver controller. 
  3. Same as step 3 in Master transmitter, check if the interrupts are clear and that the clock dividers are configured for the actual SCL.
  4. Fill the read data count into the transfer size register of the PS IIC. Enable the Hold bit if the transfer size is larger than FIFO depth.
  5. Write the address into the slave address register
  6. Wait for the data to be received by checking the RXDV bit of the status register.
    • If RXDV = 0 and any of the interrupt bits in the ISR are set then stop the transfer and report an error.
    • Similarly, if RXDV = 1 and any of the interrupt bits in the ISR are set then stop the transfer and report an error.
  7. If RXDV=1 and no errors are reported then read the data from the FIFO until status RXDV=1. If the remaining data to be received from the slave is less than the FIFO depth, clear the HOLD bit.
  8. Wait for the COMP bit to be set in ISR for completion of the transfer.
  9. The above debugging steps for the program sequence are for the default polled method.
    If using the interrupt method with the Master receiver, the differences would be as follows:
    • You would need to enable interrupts before data transmission
    • Instead of RXDV bit monitoring, you would need to check for the DATA bit in the ISR.

FAQs 

  1. What is Timeout in IIC?
    If at any point the SCL clock signal is held low by the master or the accessed slave for more than the period specified in the timeout register, a [TO] interrupt bit is generated to avoid stall conditions.
  2. How can I reset PS IIC?
    The register RST_LPD_IOU2 bits 9 and 10 are used to reset the controller
  3. Which modes are supported?
    Master mode, Slave mode, and Multi-Master mode.
    Note: you will need to maintain the same SCL frequencies in all masters in multi-master mode.
  4. Which frequencies are supported?
    100 kHz and 400 kHz only.
  5. How can users check for bus errors?
    Monitor the ISR register for ARB_LOST, NACK, RX_OVF, and RX_UNF errors on the bus.
  6. How to differentiate between DATA and COMP flags? 
    The DATA bit has a trigger in the ISR register for every 14 bytes of reading data and the COMP bit indicates completion of the transfer.
  7.  Which specification does PS IIC follow? 
    NXP specification UM10204 
  8.  What is the maximum data transmission supported?
    255 bytes

 

AXI IIC programming sequence debug: 

Users can debug the AXI IIC IP by using the following read/write operations to understand if the protocol is working.

The preferred option to get quick results is to use Dynamic programming for debugging.

 

Dynamic Read operation:

The end goal of this is to read a single register from the slave device to prove the master-slave device functionality.

  1. Write START + the Slave address with the write operation into the TX FIFO
  2. Write the Sub-register address of the slave into the TX FIFO
  3. Write RE-START + the Slave address with the read operation into the TX FIFO
  4. Write STOP + the number of bytes to be read from a slave into the TX FIFO
  5. Enable the controller using the control register
  6. Poll the status register for RX_FIFO_EMPTY to find out the data reception status (If RX_FIFO = 0 then the data is there in the receive FIFO)
  7. If there is no data in the RX FIFO and RX_FIFO_EMPTY is 1, you can follow the below steps to understand the issue:
  8. If you are not able to receive the data because the slave is not responding, it could be that there is no slave device presented with the specified address. Please double-check that the slave address is correct.
  9. If you are confident that the slave address is correct, please probe the SCL/SDA to understand whether ACK is being generated from the slave or not.
  10. If ACK is there from the slave device, please check the sub-register in the same way to debug the communication.
  11. Check the TX_FIFO_Empty flag to confirm if all of the data has been transmitted or not.
  12. If there is no problem in step 6 then you can receive the data from the slave and check if communication has been established.

 

Dynamic Write operation:

  1. Write START + the Slave address with the write operation into the TX FIFO
  2. Write the Sub-register address of the slave into the TX FIFO
  3. Write all bytes of the data except for the last byte into the TX FIFO
  4. Write STOP + the last byte of data into the TX FIFO
  5. Enable the controller using the the control register
  6. Poll the status register for TX_FIFO_EMPTY to determine the data transmission status (TX_FIFO_Empty = 1 means that the data transmission completed)
  7. If the user wants to check the write operation is proper or not can be debugged from the below points:
  8. Please check the transmit occupancy register to confirm whether all of the data has been transmitted or not.
  9. User can also do the above mentioned read operation to cross verify the write operation by reading and validating data.
  10. If ACK is there from the slave device, please also check the sub-register in the same way to debug the communication.
  11. Check the TX_FIFO_Empty flag to confirm if all of the data has been transmitted or not.
  12. If there is no problem in step 6 then you can write the data to the slave and check if communication is established.

 

Where to start with basic design testing?

  1. Bare-metal test cases:
    • Accessing the EEPROM from the PS-IIC - Users can refer to the example code to test accessing the slave via the PS IIC controller.
    • Low-level AXI IIC register access to the slave - User can use the attached example code to test the basic functionality of the AXI IIC controller.
    • Accessing the EEPROM from the AXI-IIC - Users can refer to the example code to test accessing the slave via the AXI IIC controller. 
  2. Linux test cases:

 

Clock stretching

IIC devices can slow down communication by stretching the SCL. During an SCL low state, any IIC master or slave on the bus can additionally pull-down SCL to prevent it from rising again, enabling it to slow down the SCL clock rate or to stop IIC communication for a while.

 

clock_stretch.jpg

 

How to test clock stretching with AXI-IIC:

 The purpose of the test case is to generate a clock stretching mechanism.

    Example simple hardware design:

  1. Create a Vivado hardware design with two AXI-IIC IP instances
  2. The output frequency of the two IPs is identical in this test-case.
  3. The SCL and SDA of each AXI IIC IP should be externally loop-backed i.e. SCL0 to SCL1 and SDA0 to SDA1.
  4. Once the design is ready you can export to SDK and include the source code in the below attachment.

Note: The attached example block diagram and source code have been tested on a ZCU102 board. Users can leverage this test case on their custom boards and it can also be ported to Vitis.

clock_stretch_dsgn.jpg

 

How to select a slave for the Xilinx IIC controller?

The AXI IIC and PS IIC controllers are compliant with the NXP IIC bus specification. The user must make sure that the slave device they opt for has the same timing parameters as in Table 10 on page 48 of UM10204.

Timing Parameters of the SDA and SCL bus linesTiming Parameters of the SDA and SCL bus lines

Note: PS IIC does not support Fast mode plus.