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Signal Integrity Simulation - Getting started: Part 1

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Hello and welcome back to the Hardware simulation blog series.

I hope you had a chance to go through and digest the content from the earlier post, where we discussed the basics of Signal integrity Simulations, and the models required to run them. If you haven't, I would highly recommend going over the post here before proceeding with this entry. If you are already familiar with the IBIS models and are looking at getting started with the Hyperlynx® tool, jump right in. 

In this post, we will look at how to invoke Hyperlynx®, set up a simple schematic and run some basic simulations. Hyperlynx® supports two simulation workflows.


This is used for Pre-Layout simulations and is an early simulation tool in the design cycle. It is used to evaluate what-if scenarios and to help define board parameters and routing guidelines. Simulations in LineSim are done in the Schematic GUI by creating the schematic representation of the I/O Buffers, Traces, terminations and connector/cable components.  


This is used for Post-Layout simulations to analyze the PCB design. The required nets in the PCB are selected from the layout file and are simulated like in LineSim. Because it uses the layout file containing the routing constraints along with information on the adjacent nets routing and distance, the simulations will be highly accurate.  Any violations or changes required can be explored in LineSim and fed back into the layout before signing off on the final PCB to be fabricated.

During this series, LineSim and Boardsim will be used as and when needed, depending on the topic being discussed.

Let’s get going by doing a simple simulation to get a feel for the tool. Invoke Hyperlynx®  and Choose New -> New SI Schematic and for the Waveform Viewer choose “Both” or “Oscilloscope”

fig 1.png

Hyperlynx®  supports the basic elements required for SI simulation, as shown in the below screen capture:

fig 2.png

  • Transmitters and receivers (IBIS Models)
  • Lumped Elements Resistors, Capacitors, Inductors
  • Transmission Lines
  • Simple, Microstrip, Stripline, Wire, Cable, Connector
  • Stackup and Coupled lines
  • Vias
  • S-Parameter/Spice models
  • Voltages and Ground

To create a schematic, Select “Add IC to Schematic” for Single-Ended I/O Standards or “Add differential IC to Schematic” for Differential I/O Standards.


Single-Ended Setup:

Double Click on the IC to open the “Assign Models” window. We will use Single Ended I/O Standard LVCMOS33. 

fig 4.png

  • Note: You will need to have the IBIS file (.ibs) under the “Libs” folder (C:\MentorGraphics\9.4.2HL\SDD_HOME\hyperlynx64\Libs) of Hyperlynx®  to view it in the default library selection.  You can choose to add more folders to the Model-Library file path under Setup -> Options ->Directories. Make sure to check “Add design folder” and “Add design folder subfolders” to include all the folders within the design folder.

Select the necessary settings for the model (Transmitter in this case and hence Output) and Click “OK”

fig 5.png  fig 6.png 

Click "Add transmission line to schematic" 

fig 7.png fig 8.png

Double Click on TL1 to set up the Transmission Line and select “Simple” uncoupled type, then set “Z0” -> 50 ohms, and “Delay” -> 1.000ns.

fig 9.png

Set up the Receiver by selecting the necessary Receiver IBIS Model and set the Buffer setting to Input to complete the schematic. Save the schematic setup.

fig 10.png

fig 11.png

Run Simulations, selecting the “Run Interactive Simulations and Show Waveforms” button which will open the Digital Oscilloscope window.

fig 12.png

Set the following settings in the Oscilloscope Window and Click “Start Simulation”

Operation -> Standard

Stimulus -> Global,

Oscillator -> 100 MHz, 50% Duty

IC modeling -> Typical

Thresholds for -> U2.151

Horizontal Scale -> 5ns/div

fig 13.png

The Blue Lines show the Vinh, Vinl Thresholds of U2. These are helpful when determining if receiver waveforms cross those thresholds as expected, in order for the receiver to determine if the required Logic is “Low” or “High”.  The RX waveform (Green) and TX waveform (Red) do not have clean transitions and these will be discussed in more detail in later topics in the series. 

Differential Setup: 

Double click on the IC after "Add differential IC to Schematic" to open the “Assign Models” window. We will use the Differential I/O Standard LVDS for this setup as it is one of the most commonly used Differential I/O Standards. 

fig 14.png

Select the necessary settings for the model. It is a Transmitter in this case and so the “P” suffix is selected as Output and “N” will automatically become “Output Inverted” as this is a Differential Buffer. Click “OK”

fig 15.png  fig 16.png

Click "Add transmission line to schematic" 

fig 17.png

Double Click on TL1 to set up the Transmission Line. Select “Simple” for the uncoupled type, and set “Z0” -> 50 ohms, “Delay” ->  0.5ns and Select Copy to re-use for the “N” transmission line.

fig 18.png

Add TL2, double click to Edit, and select Paste to copy the properties of TL1 to TL2.

fig 19.png

Set up the Receiver by selecting the necessary Receiver IBIS Model with the Buffer setting set to Input. This will complete the schematic.

Save the schematic setup.

fig 20.png

Add the 100-ohm Termination Resistor required for LVDS and set the value to 100 ohms by Double Clicking on the “R” symbol.

fig 21.png

Run Simulations by selecting the “Run Interactive Simulations and Show Waveforms” button. This will open up the Digital Oscilloscope window. Enter the settings below in the Oscilloscope Window and Click “Start Simulation”:

Operation -> Standard

Stimulus -> Global,

Oscillator -> 400 MHz, 50% Duty

IC modeling -> Typical

Thresholds for ->  U2.631P

Horizontal Scale -> 1ns/div

Vertical Scale -> 500mv/div

Vertical Position -> -900 mv/div

The signal probing can be done either “At the Pin” or “At the die”.

Probing at the pin: 

This places the Simulation probe at the pin and represents what you would see in a lab oscilloscope if you physically probed at the pin on the board. “Purple” is the Differential probe waveform.

fig 22.png

Probing at the die:

This places the Simulation probe inside the die and represents what the die sees, which cannot be probed on the board.

fig 23.png

Refer to (Xilinx Answer 57566) for more details on probing for Internal and External terminations. 

Defining Stackup

The layer stackup for the PCB needs to be defined for the dielectric material, metal type, arrangement of signal and plane layers in a board among other items. Setting this up before running simulations helps to mimic the PCB, along with various characteristics such as trace impedance, trace separation and other parameters.

Hyperlynx®  provides a Stackup Editor that consists of a spreadsheet based view where you can input values along with a picture pane to visualize the stackup. The editor can be accessed by selecting Setup -> Stackup Edit or the “Edit Stackup” Button as shown below:

fig 24.png

fig 25.png

As seen in the above figure, the Editor has various tabs and a quick description of the tabs. 

Basic: Define stackup information by adding/deleting layers, and setting measurement units (English/Metric), and metal thickness (Thickness/Weight)

Dielectric: Define the dielectric characteristics of the stackup such as technology, loss tangent, and thermal conductivity. There is an option to calculate the dielectric constant for the metal layer from surrounding dielectric layers.

Metal: Define the metal characteristics such as type of Metal (Copper/ Aluminum/ Tin etc..), Thickness, and other properties of the metal.

Z0 Planning: Define the characteristic impedance of the stackup. This planning tab is one of the most useful tabs as it enables you to calculate the optimal data when you need a specific target impedance for single and differential pair traces.              

Manufacturing: Define metal surface roughness and trace etch parameters.

Custom View: Used to set up a customized view of the spreadsheet information derived from the other tabs and to tweak per user preference.

Refer to the Hyperlynx User Guide for advanced details on these tabs.

Let’s go ahead and set up the stackup for a Z0 of 50 ohms, as it is the most commonly used value. The trace impedance is determined by the “Width” of the trace, “Height” above a reference plane, or the “Dielectric thickness” and “Dielectric constant”. There are various methods to set the impedance in the stackup editor, however we will use the Metal tab to quickly set the required impedances. 

Open the Stackup Editor and select View -> Calculate Z0 (enable this if it is not enabled). This enables automatic characteristic impedance calculation by the tool based on the stackup.

fig 26.png

Select the Metal tab and set the Thickness of Dielectric as below. Note Z0 for the signal layers. 

fig 27.png

Ensure that the “No errors found in stackup” message is displayed in the Picture pane after you modify the parameters.

Use the Z0 Planning Tab to check the required trace width and separation needed for a target impedance of a single trace and differential pair. This is helpful because interfaces/protocols have different impedance requirements and this tab helps in understanding the required width or separation needed to meet those specifications.

  1. For Single Trace: Select Single trace from the Plan for drop-down list and input 50,60, 40,50 in the Target Z0 value column for the signal layers and then press Enter. The Trace widths required to achieve these impedances are updated.

fig 28.png  

     2. For Differential pair: Select 'Differential pair' from the 'Plan for' drop-down list, 'Solve for width' in Strategy and input 100,90,80,100 in the Target Z0 value column for the signal layers. Now press Enter. The Trace widths required to achieve these impedances are shown. The strategy for trace separation for differential can also be followed to meet the Target Z0, by choosing Solve for Separation. The strategy also includes an option to use both, i.e. Solve for width and Solve for Separation, and results shown in the Z0 Curve column.

fig 29.png

Now that the stackup is created, it can be exported to be reused for future designs and simulations to save time. Select File -> Export -> save as <desired_name>.stk file

Click OK to close out the Editor.

  • Note: The stackup creation for a PCB design is one of the most important and critical steps during the design process and requires time and effort based on complexity. “What If” analysis can be used in the editor based on design and manufacturing requirements to achieve a finalized stackup. However, the steps described above are designed to give an insight into the editor and to provide a stackup for future designs and simulations in the series only. They are not based on any design parameters.

I will now leave you to use the steps we discussed above to familiarize yourself with the tool and interface.

In the next post, we will cover a few more features of Hyperlynx®, and that will set you up with the basics for using the tool.

Until then, have fun playing around with the tool and the various settings, and I will see you next time.