cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

UVM (Universal Verification Methodology) Support in Vivado Simulator

Moderator
Moderator
6 2 2,599

The Vivado Integrated Design Environment supports Universal Verification Methodology (UVM) when using Vivado Simulator.

The UVM version 1.2 library is precompiled and is available with Vivado.

To use UVM in project mode please follow the below steps to create an example design test case.

(Attached is a simple example which you can download and unzip).

  1. Create a new RTL project in Vivado 2019.2.
  2. Add the directories “src” and “verif” to the project by clicking on Add Directories.
    Specify that the UVM verification files are for simulation only.2.JPG3.JPG
  3. Select the part/board required for the project and then click on next.
  4. Check the project summary and click on Finish.5.JPG
  5. Once the project is created with the added sources from the “src” and “verif” directories, go to Settings -> Simulation.
    Add the “-L UVM” switch to xsim.compile.xvlog.more_options which can be found under the compilation tab and to xsim.elaborate.xelab_more_options  under the Elaboration tab (See the screen captures below).
    This is needed to use the pre-compiled UVM library.

    6.JPG7.JPG

     

    We can also set the following properties through the Tcl console:

    set_property -name {xsim.compile.xvlog.more_options} -value {-L uvm} -objects [get_filesets sim_1]
    set_property -name {xsim.elaborate.xelab.more_options} -value {-L uvm} -objects [get_filesets sim_1]

    These steps are documented in Appendix C of (UG900).

  6. After adding the above switch make sure that the “adder_4_bit_tb_top.sv” file is selected as the top module and then run simulation.

    Simulation should run without any issues although the Vivado hierarchy sources window will show syntax errors on the files.

    You can ignore the syntax errors regarding UVM in Hierarchy window and Vivado Text Editor as UVM support is added for simulator alone in Vivado 2019.2.

    UVM support for HSV will be coming in a future release.

    8.jpg

Below are the steps to use UVM in Non-Project/Batch Mode:

  1. Invoke Vivado 2019.2.

    source <Vivado_install_path>/Xilinx/Vivado/2019.2/settings64.sh
  2. To run the Simulation in non-project mode, change the current working directory to the “run” folder.

    cd ./Adder_4_bit/run
  3. For standalone simulation in Vivado you can source run_xsim.csh on Linux and run_xsim.bat on windows or source run.tcl using the below command in Linux/Windows.

    Vivado –mode batch –source run.tcl
  4. Once the simulation is finished we can observe the UVM test results in the Shell or command prompt as shown below:

    12.JPG11.jpg

Directory Structure of both project and non project mode:

The "src" and "verif" folders contain Design and verification environment related files.

Run is the location to run simulation in Non project mode.

UVM_test is for Project Mode simulation in XSIM.

 

2 Comments
Explorer
Explorer

Hi @bandi ,

thanks for the post very much, I do appreciate it,  but this example project does not seem to work yet.  I use Vivado v2020.1 .

"You can ignore the syntax errors regarding UVM in Hierarchy window and Vivado Text Editor as UVM support is added for simulator alone in Vivado 2019.2. UVM support for HSV will be coming in a future release. "

I was hoping 2020.1 would help this issue, but apparently we need to wait.

However, I launched simulation with the following result:


UVM_FATAL @ 0: reporter [NOCOMP] No components instantiated. You must either instantiate at least one component before calling run_test or use run_test to do so. To run a test using run_test, use +UVM_TESTNAME or supply the test name in the argument to run_test(). Exiting simulation.
UVM_INFO /proj/xbuilds/SWIP/2020.1_0223_2001/installs/lin64/Vivado/2020.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv(13673) @ 0: reporter [UVM/REPORT/SERVER] [UVM/RELNOTES] 1
[NOCOMP] 1
** Report counts by id
UVM_FATAL : 1
UVM_ERROR : 0
UVM_WARNING : 0
UVM_INFO : 1
** Report counts by severity

--- UVM Report Summary ---


$finish called at time : 0 fs : File "C:/Xilinx/Vivado/2020.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv" Line 18538
xsim: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 2964.070 ; gain = 0.000
INFO: [USF-XSim-96] XSim completed. Design snapshot 'adder_4_bit_tb_top_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:25 ; elapsed = 00:03:16 . Memory (MB): peak = 2964.070 ; gain = 0.000
run 1 ms

 

Please help us newbies with some further info.

Thank you indeed.

Miklos

 

 

 

 

 

 

 

Newbie
Newbie

Hi,

In windows:


1/ run Vivado 2020.1 Tcl Shell
(it is installed with vivado, just type cmd after you press [win] button)
2/ go to dir:

/Adder_4_bit/run

 3/ source run.tcl

Hopefully you end up with: 0 uvm fatals.

However GUI gives me the same answer as to @mbence76, which is strange since it should go through the same flow. In case of the batch version UVM_TESTNAME flag is working just fine.