The Vivado Integrated Design Environment supports Universal Verification Methodology (UVM) when using Vivado Simulator.
The UVM version 1.2 library is precompiled and is available with Vivado.
To use UVM in project mode please follow the below steps to create an example design test case.
(Attached is a simple example which you can download and unzip).
Create a new RTL project in Vivado 2019.2.
Add the directories “src” and “verif” to the project by clicking on Add Directories. Specify that the UVM verification files are for simulation only.
Select the part/board required for the project and then click on next.
Check the project summary and click on Finish.
Once the project is created with the added sources from the “src” and “verif” directories, go to Settings -> Simulation. Add the “-L UVM” switch to xsim.compile.xvlog.more_options which can be found under the compilation tab and to xsim.elaborate.xelab_more_options under the Elaboration tab (See the screen captures below). This is needed to use the pre-compiled UVM library.
We can also set the following properties through the Tcl console: