cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Understanding the new PL PCIE IP Generation flow for Versal ACAP Devices

deepeshm
Xilinx Employee
Xilinx Employee
0 0 394

A PL based PCIe base IP consists of PCIE PHY, GT QUAD and PCIe MAC. In addition to these, in QDMA/XDMA/Bridge IP cores, it consists of a corresponding additional wrapper module for the respective IP.

In PL PCIe for Versal™ ACAP, the way the PCIE IP as a whole is integrated with different components has changed compared to previous devices such as UltraScale and UltraScale+ devices. The below are the major changes that went into PL based PCIe IP in Versal ACAP devices.

  • GT components are updated from Common/Channel to a quad granularity.
  • GT wizard flows are modified to use the Vivado® IP integrator.
  • Only the Vivado IP integrator-based block design flow is currently supported with manual or automatic connectivity.
  • The required GT and PHY IP blocks for Versal ACAP PL PCIe interfaces are outside of the Versal ACAP PL PCIe4 IP.

 

This blog illustrates the difference in the IP generation flow between Versal ACAP and UltraScale+ devices.  The screenshots provided below are from Vivado 2020.2. Below are the key takeaways covered in this entry:

  • How PCIe PHY, GT and PCIe MAC are integrated in UltraScale+ Integrated  Block (PCIE4) for PCI Express IP
  • How the Channel based GT LOC constraints are applied in UltraScale+ Integrated Block (PCIE4) for PCI Express IP
  • The generated Example Design source hierarchy in UltraScale+ Integrated Block (PCIE4) for PCI Express IP
  • How all of the blocks mentioned above are separated and connected in Vivado IP integrator in  Versal ACAP Integrated Block for PCI Express IP
  • QUAD based GT LOC constraints in the top level XDC file of the generated example design for Versal ACAP Integrated Block for PCI Express IP
  • How PCIe PHY, GT, PCIe MAC and QDMA wrapper modules are integrated in Vivado IP integrator for Versal ACAP devices.

 

Generating UltraScale+ Integrated Block (PCIE4) for PCI Express IP

 

IP Configuration

 

2.png

Generated Core Hierarchy

 

3.png

The hierarchy above shows both GT and PCIe PHY as sub modules in the PCIe IP core.

 

GT Channel Constraint

 

4.png

Note: The GT LOC constraints are defined in the GT XDC file. The top level XDC GT LOC constraint does not override the constraint defined in this XDC file.

If the user wants to change the GT LOC constraints, they need to change it in the GT XDC file shown above or set the 'Disable GT Channel LOC Constraint' option to true in the core configuration GUI as shown below. The latter will allow users to define GT LOC constraints in the top level XDC file.

 

5.png

Example Design Hierarchy

 

The screenshot below shows the source file hierarchy of the generated example design for the UltraScale+ Integrated Block (PCIe4) for PCI Express IP.

 

6.png

Generating Versal ACAP Integrated Block for PCI Express IP

 

IP Configuration

 

7.png

Generated Core Hierarchy

The below screen capture shows the Versal ACAP Integrated Block for PCI Express IP generated in Vivado for the PCIe IP configuration shown above.

Please note that the source hierarchy does not include GT and PCIe PHY. This is a new change introduced in Versal ACAP devices. The GT and the PCIe PHY are outside of the PCIe MAC. 

There are essentially two ways to generate the full IP (i.e. PCIe MAC connected with PCIe PHY and GT).

  • Generate Example Design - This will generate the example design and the necessary module instantiation in the IP Integrator is done under the example design wrapper.
  • Add the Versal ACAP Integrated Block for PCI Express IP in the IP Integrator canvas and run 'Block Automation'.

8.png

Example Design Hierarchy

 

The below screen capture shows the example design hierarchy for Versal ACAP Integrated Block for PCI Express IP.

The IP Integrator design is included as a submodule in the example design.

 

9.png

The IP Integrator design consists of GT, PCIe PHY and PCIe MAC as separate blocks as shown in the screenshot below.

 

1.png

 

GT QUAD Constraint

 

The GT LOC constraints are included in the top level XDC file.

 

10.png

Generating IP without Example Design

 

The full IP can be generated without generating the example design.

To do so, add the PCIe MAC (pcie_versal_0) in the IP Integrator canvas and click on 'Run Block Automation' as shown below.

11.png

12.png

 

13.png

The pcie_versal_0_support block shown above consists of the GT QUAD and PCIe PHY as shown below.

 

14.png

 

QDMA Example Design Hierarchy in UltraScale+ Devices

 

15.png

 

QDMA Example Design Hierarchy in Versal ACAP Devices

 

16.png

 

The full QDMA IP can be generated by opening the example design or by running Block Automation.

 

17.png

The qdma_0_support IP consists of GT QUAD, PCIe PHY and PCIe MAC. The internal schematic of the qdma_0_support block is shown below.

 

19.png