Create a Project in Vivado targeting a Versal device.
Create a block design.
Add the Advanced IO Wizard to the canvas.
Double Click on the IP to Customize it.
Setting up the Advanced IO Wizard
By default, the Advanced IO Wizard Basic tab is set up for Source Synchronous RX Only with a default speed of 1000Mbps, PLL Input of 100MHz and a Serialization factor of 8.
We will continue with the default options in this example.
If you are choosing different options for Interface Speed, PLL Input, or Serialization you will need to make changes in the testbench. We will discuss how to do this later.
Select Reduce Control signals to reduce the number of FIFO Control signals.
Select Enable Delay Control Signals to expose the Delay controls.
Leave Enable BLI Logic selected as this helps with meeting timing from the XPIO to fabric.
Add the IO Std of your choosing. In this example I chose LVDS15.
We are leaving the Number of Banks as 1 as the I/O will be placed in one bank.
Pin Configuration Tab
On the Pin Configuration Tab I set the Number of Data Channels to 8 and the testbench is set for 8 differential pairs.
The Strobe and Data signals can be changed but we are leaving them at their defaults.
Select OK and Generate Output products:
Connecting the Wizard
The Advanced IO Wizard requires a CTRL_CLK that can be sourced from the PLL in the core. Connect the bank0_pll_clkout0 to the ctrl_clk.
The FIFO_RD_EN can be derived from NOT FIFO_EMPTY. In the following code, we take both the Interface Ready signal (INTF_RDY) and the FIFO_EMPTY to wait until the Interface is ready and the FIFO is not empty to assert the FIFO_RD_EN.
Add the Verilog code to a file and select it in Vivado. If you are not familiar with IP Integrator you can add the RTL into the BD by selecting the file, right clicking and selecting Add Module to Block Design.
Make the Data, Strobe, RST, EN_VTC, INTF_RDY and delay line signals External.
Make the data_to_fabric_data_pin External.
Add a Utility Buffer which defaults to IBUFDS, connect the IBUF_OUT to the bank0_pll_clkin port, and make the input of the Utility Buffer External.
Validate the Block Design and fix any warnings.
Attached at the bottom of this Blog entry is a bd.tcl for your reference.
Note: all Versal designs must have a Control, Interface and Processing Systems IP in order for the device to boot properly. We are only simulating this design so we are not including a CIPS. If you intend to put the design on hardware you must include the CIPS.
Now create the HDL Wrapper.
We need to add the testbench to the project and the wave configuration file.
Save the testbench and script to the one location and source the script. Alternatively you can add the testbench in the GUI and change the Elaborate Level to all, then add the WFCG.
The inputs to the DUT are the input clock, strobe and data.
When simulating the Advanced IO Wizard we need to wait for BISC to complete i.e. for INTF_RDY to assert.