The UHD-SDI Subsystems RX/TX IP cores have several example designs available at the time of writing, but all are a variation of a pass-through design. For information on these designs, please see (PG289) and (PG290).
This Blog entry will instead outline how to create and run a TX only design targeting the ZCU106 development board.
Note: This design is provided as-is with no guarantee. It was built outside of normal release/test flows for instructional purposes.
This design is not supported through the SR portal. If you have issues with this design, please create a forum post on the Xilinx Video Forums board.
This design showcases how an SDI TX system can be built and run on a ZCU106 Rev 1.0 board using the Vivado 2019.2 toolset.
The design was created based on the pass-through design released in the Product Guide then updated to be for TX only. Its purpose is to show a quick implementation of the UHD-SDI TX subsystem and UHD-SDI GT in TX only mode.
It includes the following:
A Zynq Subsystem Instantiation to control the IP
GPIOs to monitor statuses (left over from the original pass-through design)
A TPG to create video data
A subset converter to convert the TPG from 8 BPC to 10 BPC
FIFO (from the original pass-through design)
UHD-SDI TX subsystem
It was tested for functionality using an Onmitek4K Ultra.
Using the provided Script to create the bitstream
From the command line or the Vivado terminal, run the Tcl script from the directory:
Vivado -source v_smpte_uhdsdi_rx_ss_0_ex.tcl
Wait for the script to complete and then run Vivado to generate a bitstream. This can be done in script mode or by opening the Vivado GUI and following the typical Synthesis, Implementation, Bitstream generation flow.
After the bitstream is generated, export the XSA file.
How to create the ELF file from the XSA:
Open the Vitis GUI.
Create a new platform project and point to the XSA exported from the Vivado project.
Build the BSP, using the build tool.
Once the BSP has been built, select Import Examples from the Drivers.
Import the xsdi_example
Replace the /src files xsdb_* with the files located in /SW. These files have been edited for the TX only hardware design.
Build and test. The image below shows the UART console. Note: for more information on Building and Testing, see the default example designs documented in (PG289) and (PG290).