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Video Blog - Implementing the UHD-SDI TX subsystem in a TX only design on a ZCU106 board

samk
Moderator
Moderator
5 7 2,481

The UHD-SDI Subsystems RX/TX IP cores have several example designs available at the time of writing, but all are a variation of a pass-through design. For information on these designs, please see (PG289) and (PG290).

This Blog entry will instead outline how to create and run a TX only design targeting the ZCU106 development board.

 

 

samk_0-1604615662095.png

 

Note: This design is provided as-is with no guarantee. It was built outside of normal release/test flows for instructional purposes.

This design is not supported through the SR portal. If you have issues with this design, please create a forum post on the Xilinx Video Forums board.

 

This design showcases how an SDI TX system can be built and run on a ZCU106 Rev 1.0 board using the Vivado 2019.2 toolset.

The design was created based on the pass-through design released in the Product Guide then updated to be for TX only. Its purpose is to show a quick implementation of the UHD-SDI TX subsystem and UHD-SDI GT in TX only mode.

It includes the following:

  • Reset Functionality
  • A Zynq Subsystem Instantiation to control the IP
  • GPIOs to monitor statuses (left over from the original pass-through design)
  • A TPG to create video data
  • A subset converter to convert the TPG from 8 BPC to 10 BPC
  • FIFO (from the original pass-through design)
  • UHD-SDI TX subsystem
  • UHD-SDI GT

It was tested for functionality using an Onmitek4K Ultra.

2020-11-24 15_37_55-xcoapps63_6 (xcoapps63_6 (samk)) - VNC Viewer.png

Using the provided Script to create the bitstream

  1. From the command line or the Vivado terminal, run the Tcl script from the directory:
    Vivado -source v_smpte_uhdsdi_rx_ss_0_ex.tcl
  2. Wait for the script to complete and then run Vivado to generate a bitstream.
    This can be done in script mode or by opening the Vivado GUI and following the typical Synthesis, Implementation, Bitstream generation flow. 
  3. After the bitstream is generated, export the XSA file.

 

How to create the ELF file from the XSA:

  1. Open the Vitis GUI.
  2. Create a new platform project and point to the XSA exported from the Vivado project.
    samk_0-1604615769518.png

     

    samk_1-1604615769527.png

     

  3. Build the BSP, using the build tool.
    samk_2-1604615769534.png

     

  4. Once the BSP has been built, select Import Examples from the Drivers.
    samk_3-1604615769536.png

     

  5. Import the xsdi_example
    samk_4-1604615769538.png

     

  6. Replace the /src files xsdb_* with the files located in /SW.
    These files have been edited for the TX only hardware design.
  7. Build and test. The image below shows the UART console.
    Note: for more information on Building and Testing, see the default example designs documented in (PG289) and (PG290).

samk_5-1604615769541.png

 

 

Tags (1)
7 Comments
skatepoiser
Newbie
Newbie

I am having issue with the TPG. I was trying to validate the design but I am getting a critcal error stating that the TDATA size is different. I went ahead and change the bus width but i am having issue still when i am running the program. What is the best fix for this?

samk
Moderator
Moderator

Hi @skatepoiser<

Can you share the error message?
Also, can you provide more information on the issues you are having when running the program? Errors/messages etc.


CtrpDn
Visitor
Visitor

Hi,

I am using your design example with: ZCU106 board rev 1.0 and a Magwell USB capture SDI Gen 2 (Supports up to 2K).

Working with 2019.2 version.

After running the example I can see from the console prints that for:

*6G and 12G I got locked = 1, underflow = 0 and overflow = 0. Can not capture with the Magwell device - resolutions are not supported.

*3G and HD I got locked = 1, underflow = 1 and overflow = 0. From the ILA it seems that the FIFO "almost_full" flag is stuck at '1', I tried to enlarge FIFO depth but it doesn't help. I can capture the video with the Magwell device for example with 1920/1808@60 resolution but only for TPG patterns XTPG_BKGND_COLOR_BARS, XTPG_BKGND_PBRS, XTPG_BKGND_CHECKER_BOARD and XTPG_BKGND_TARTAN_COLOR_BARS. For the other patterns I just get a black image.

Can any one help to understand:

* Why the underflow = 1 for 3G/HD?

* Why the FIFO "almost_full" flag stuck at '1'?

Thanks!

 

grw123
Observer
Observer

First off - thanks for posting this. But I'm having a few issues;

I've been a bit naughty and upgraded the design to 2020.1. I can build fine in Vivado after IP upgrade.

However, the application code halts operation in function XV_SdiTxSs_StreamStart, specifically while configuring the VTC.
Looking at the memory space in the debugger, none of the VTC registers at 0x8001_0000 and above are not readable. So it is not surprising that the config of the VTC fails as it is trying to access this address space.
Looking in the UHDSDI block the SDI_TX and VTC blocks use the same clock, reset and control bus, so as I can read one I can't understand why I can't read the other.

I note that the block design has s_axi_aclken input port open. I assume this is forced active by default, and as the sub-block is not editable then I can not hardwire to be certain.

Has anyone else had this issue, and did you resolve it?

grw123_0-1615552589068.png

grw123_1-1615552793806.png

 

 

samk
Moderator
Moderator

Hi @CtrpDn,

The SDI solution is one directional meaning that a sink can not put backpressure on a source. 
Based on this we can rule the backpressure back to the data flow within the FPGA it's self. 

Have you edited the project or are you using the project as delivered? If you are using the project as is, I can take a look on my side to see if there are any existing issues. 
If you have made any edits, are you changing the TPG resolution and the SDI resolution correctly? These need to be the same or you may run into overflow/underflow issues with the AXI->Native mode->SDI bridge.

samk
Moderator
Moderator

Hi @grw123,

First of all, good job updating to 2020.1. Are you able to share your design with me directly? I can send you an encrypted link and run on my side to see if I have the same issue.

There have been a few reports of the SDI designs failing on some ZCU106 boards and not others. I think there may be a reset/clocking issue we are dealing with that is causing the VTC to lock up. **This IP is only reset at initialization, and if there is an issue it can not be reset.

To help verify if this is a board level issue or design issue, can you test with the released 2020.1 passthrough design from the UHD-SDI PG?


Thank you,

Sam

samk
Moderator
Moderator

For anyone with questions, please start a thread on the Video Forums. The forum is actively monitored and you will likely get a reply much faster. Replying to this thread requires that I check this thread, which I may not do on a regular basis.

Forum to post questions:  https://forums.xilinx.com/t5/Video-and-Audio/bd-p/DSPTOOL